MN6155 Datasheet, PDF (3/9 Pages) Panasonic Semiconductor – PLL LSI with Built-In Prescaler

For Communications Equipment
MN6155
Pin Descriptions
Pin No. Symbol
1
X_IN
2
X_OUT
3
FV
4
V_DD
5
D_OP
6
V_SS
7
V_CP
8
F_IN
9
CLK
10
DATA
11
LE
12
PS
13
FR
14
LC
15
RSL
16
R_IN
Function Description
Crystal oscillator connection pins:
X_IN =Oscillator circuit input pin;
(X_IN is attached to a pull-up resistor when the PS or RSL pin is at "L" level.)
X_OUT=Oscillator circuit output pin.
Frequency divider output signal in comparator stage.
Phase comparator input monitor.
Power supply
Low-pass filter connection pin. Use a passive filter.
Ground
Power supply pin for built-in charge pump
Frequency divider input pin in comparator stage.
Shift register clock input pin.
The chip latches data at the rising edge of the CLK signal.
Shift register data input pin.
The final two bits in the data select the write latch:
"11" for R-latch; "01" for N-latch.
Load enable signal input pin.
This is the latch-write-enable signal. It is at "H" level for write.
Power save control signal input pin.
"H" level input starts the frequency divider and places the chip in operational
mode. "L" level input places the chip in standby mode, which saves power.
The chip switches the internal charge pump output to the H-z state and the loop
is opened.
Reference frequency divider output signal.
Phase comparator input monitor.
Charge pump control signal output pin.
When frequency divider operation is stopped, this pin is at "L" level, the
internal charge pump output is in the high-impedance state, and the loop is opened.
Reference signal selection pin.
"H" level selects self-excited oscillator (X_IN and X_OUT).
"L" level selects external oscillator (R_IN).
External reference oscillation input pin.
This pin is attached to a pull-up resistor when the PS pin is at "L" level or the
RSL pin is at "H" level.