MN195001 Datasheet, PDF (4/6 Pages) Panasonic Semiconductor – Single-Chip Fax Engine LSI

MN195001
Pin Descriptions
Func-
tional Symbol
Pin No.
I/O
Group
A0 to 23 128 to 114, 111 to 103 O
MD0 to 7
8 to 1
I/O
RD
16
O
WR
15
O
R/W
17
I
CX
11
I
SCX2
10
I
SYNCA
9
O
HDRES
12
I
MOD0 to 3 42 to 45
I
HALT
19
I
BA
18
O
IREF0
38
AI
IREF1
37
AI
TXLPIN
36
AI
TXOUT
34
AO
RXL
32
AI
IREF2
31
AI
RXLPIN
30
AI
HPOUT
29
AO
AGCIN
28
AI
AGCOUT
27
AO
SHIN
26
AI
VREFH
40
AI
VREFL
41
AI
PLSD
23
O
SO to 15
46 to 61
I/O
UC0 to 3
99 to 102
O
IRO1 to 4
67 to 70
I
U1ST
62
I
U1RD
63
I
U1RCK
64
I
U1SD
65
O
U1TCK
66
I/O
U2ST
71
I
U2RD
72
I
U2RCK
73
I
U2SD
74
O
U2TCK
75
I/O
SH1 to 4
85 to 82
O
MTA1 to 4
92 to 89
O
For Communications Equipment
Function Descreption
External memory address bus
External memory data bus
External memory read signal
External memory write signal
External memory read/write control
Basic clock input
Basic clock frequency selection
System clock output
Reset signal
Mode setting inputs
HALT signal for internal digital signal processor
External memory bus available signal
D/A converter input
Reference voltage for transmit circuits
Transmit low-pass filter input
Analog transmit signal output
Analog receive signal input
Reference voltage for receive circuit
Receive low-pass filter input
Receive high-pass filter output
Receive automatic gain control input
Receive automatic gain control output
A/D converter sample-and-hold circuit input
A/D converter reference "H" level
A/D converter reference "L" level
External amplifier gain control signal
General-purpose I/O port
Programmable chip select
External interrupts
USART (CH1) external synchronization clock
USART (CH1) receive data
USART (CH1) receive clock
USART (CH1) transmit data
USART (CH1) transmit clock
USART (CH2) external synchronization clock
USART (CH2) receive data
USART (CH2) receive clock
USART (CH2) transmit data
USART (CH2) transmit clock
Thermal head control signals
Motor A control signals