MN195001 Datasheet, PDF (1/6 Pages) Panasonic Semiconductor – Single-Chip Fax Engine LSI

For Communications Equipment
MN195001
Single-Chip Fax Engine LSI
Overview
The MN195001 reduces to a single chip CPU functions
related to facsimile control, peripheral device control
functions, and modem functions. The last include
complete fax/modem support for the ITU-T G3
recommandations V.29, V.27ter, and V.21 Channels 1
and 2.
The MN195001 consists of the following blocks: digital
signal processor (DSP), facsimile peripheral circuits,
analog circuits, DTE interface, clock generator, and dual-
port RAM. Changing the contents of an external ROM
tailors the chip for a wide variety of facsimile applications.
Features
Digital signal processor (DSP) block
• Micro ROM: 4096 × 32 bits
• Data RAM: 512 × 16 bits × 2 sets
• Machine cycle: 90 ns
• Parallel multiplier:
16 bits × 16 bits × → 32 bits
• Arithmetic and logic unit (ALU): 32-bit
Facsimile peripheral circuit block
• Scanner/plotter interface
• Two USART channels
• Two motor control channels
• One thermal head control channel
• Programmable chip select
Analog circuit block
• Built-in 8-bit D/A converter, A/D converter, and
filters
DTE interface block
• Built-in 8-bit I/O interface and serial interface
Clock generator block
• Sampling clock and baud rate clock generators
Dual-port RAM block
• 1024 × 8 bits
Single 5 volt power supply
Applications
Facsimile equipment