MN3881S Datasheet, PDF (3/4 Pages) Panasonic Semiconductor – PAL-Compatible CCD Video Signal Delay Element

CCD Delay Line Series
Application Circuit Example
10µF
–+
0.1µF
MN3881S
0.01µF
Auto bias circuit
VINC 16
0.01µF
Charge input
block
CCD 567 stages
Charge
Resampling output ² VOC
detection block amplifier
øS driver
ø1 driver
ø2 driver
øR driver
øSH driver
øSH driver
Timing adjustment
XI ¹³
1000pF
Waveform amplifier
adjustment block
1/2nd frequency
doubler
Timing adjustment
øS driver
ø1 driver
ø2 driver
øR driver
øSH driver
øSH driver
VINY ⁹
–+
0.47µF
Auto clamp circuit
Charge input
block
CCD 566.5 stages
Charge
detection block
Resampling output ^{7 VOY}
amplifier
0.01µF
Note: If the capacitor attached to pin 5 has a polarity, attach the negative pole to pin 5.
0.01µF
3