MN103SFM8K Datasheet, PDF (11/25 Pages) Panasonic Semiconductor – 32-bit Single-chip Microcontroller

1.3.3 Pin Functions
Table:1.3.2 Pin Functions
Name
VDD
VDD
VDD
VDD
TQFP 48
Pin No.
I/O
12
-
31
54
76
Other Function
-
VDD2
33
VSS
10
VSS
29
VSS
56
VSS
78
VPPEX
30
OSC1
28
OSC0
27
NRST
39
-
-
-
-
-
input -
output
input -
P10
34
I/O
IRQ04/ EXTRG0
P11
35
IRQ05/ EXTRG1
P12
36
IRQ06
P13
37
IRQ07
P14
38
IRQ08
P16
40
TM7IO
P17
41
SBO2
P20
42
I/O
SBT2
P21
43
SBI2
P22
44
SBO1
P23
45
SBT1
P24
46
SBI1
P25
47
SBO0
P26
48
SBT0
P27
49
SBI0
P31
50
I/O
TM1IO
P32
51
TM2IO
P33
52
TM3IO
P34
53
TM4IO
P35
55
TM5IO
P36
57
TM8AIO
P37
58
TM8BIO
MN103SFM8K
32-bit Single-chip Microcontroller
PubNo. 232M8-011E
Function
Description
Power supply pin
Power supply pin
Power supply pin
Power pins for 5 V, digital IO
Apply 5 V to all of pins and connect capacitor
of over 10 μF between all of the VDD and
VSS pins.
It is recommended that total capacitance
between all of the VDD and VSS is more than
10-times capacitance between all of the
VDD2 and VSS.
Power pins for 1.8 V, digital IO
Connect capacitor of over 1 μF between all of
the VDD2 and VSS pins.
GND for digital
Power supply pin
Clock input pin
Clock output pin
Reset pins
(negative logic)
I/O port 1
I/O port 2
Power for flash EEPROM
Connect with VDD.
Extend ceramic or crystal oscillators or input
a clock to OSC1.
This pin resets the chip when power is turned
on and contains an internal pull-up resistor.
Setting this pin “L” level initializes the internal
state of the device. Thereafter, setting the
input to “H” level releases the reset. The
hardware waits for the system clock to
stabilize, and processes the reset interrupt.
Connect capacitor of over 0.1 μF between
NRST and VSS pins.
7-bit CMOS I/O ports.
Each bit can be set individually as either
input or output by the P1DIR register.
Pull-up resistor for each bit can be selected
individually by the P1PLU register.
At reset, the input mode (P10 to P14, P16,
P17) is selected, and pull-up resistor is
disabled.
8-bit CMOS I/O ports.
Each bit can be set individually as either
input or output by the P2DIR register.
Pull-up resistor for each bit can be selected
individually by the P2PLU register.
At reset, the input mode (P20 to P27) is
selected, and pull-up resistor is disabled.
I/O port 3
7-bit CMOS I/O ports.
Each bit can be set individually as either
input or output by the P3DIR register.
Pull-up resistor for ech bit can be selected
individually by the P3PLU register.
At reset, the input mode (P31 to P37) is
selected, and pull-up resistor is disabled.
Publication date: August 2014