N25S818HA Datasheet, PDF (9/15 Pages) ON Semiconductor – 256Kb Low Power Serial SRAMs 32K × 8 bit Organization

N25S0818HA
WRITE Operations
The serial SRAM WRITE is selected by enabling CS low. First, the 8-bit WRITE instruction is transmitted
to the device followed by the 16-bit address with the MSB being a don’t care. After the WRITE instruction
and addresses are sent, the data to be stored in memory is shifted in on the SI pin.
If operating in page mode, after the initial word of data is shifted in, additional data words can be written as
long as the address requested is sequential on the same page. Simply write the data on SI pin and
continue to provide clock pulses. The internal address pointer is automatically incremented to the next
higher address on the page after each word of data is written in. This can be continued for the entire page
length of 32 words long. At the end of the page, the addresses pointer will be wrapped to the 0 word
address within the page and the operation can be continuously looped over the 32 words of the same
page. The new data will replace data already stored in the memory locations.
If operating in burst mode, after the initial word of data is shifted in, additional data words can be written to
the next sequential memory locations by continuing to provide clock pulses. The internal address pointer
is automatically incremented to the next higher address after each word of data is read out. This can be
continued for the entire array and when the highest address is reached (7FFFh), the address counter
wraps to the address 0000h. This allows the burst write cycle to be continued indefinitely. Again, the new
data will replace data already stored in the memory locations.
All WRITE operations are terminated by pulling CS high.
Word WRITE Sequence
CS
SCK _{0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31}
Instruction
16-bit address
Data In
SI 0 0 0 0 0 0 1 0 15 14 13 12 ... 2 1 0 7 6 5 4 3 2 1 0
SO
High-Z
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