CAT5132ZI-10-GT3 Datasheet, PDF (9/14 Pages) ON Semiconductor – 16 Volt Digitally Programmable Potentiometer with 128 Taps and I2C Interface

CAT5132
Wiper Control Register (WCR) Description
The CAT5132 contains a 7-bit Wiper Control Register
which is decoded to select one of the 128 switches along
its resistor array. The WCR is a volatile register and is
written with the contents of the nonvolatile Data Register
(DR) on power-up. The Wiper Control Register loses its
contents when the CAT5132 is powered-down. The
contents of the WCR may be read or changed directly by
the host using a READ/WRITE command after addressing
the WCR (see Table 1 to access WCR). Since the
CAT5132 will only make use of the 7 LSB bits (The first
data bit, or MSB, is ignored) on write instructions and will
always come back as a “0” on read commands.
A write operation (see Table 3) requires a Start condition, followed by a valid slave address byte, a valid address byte
00h, a data byte and a STOP condition. After each of the three bytes the CAT5132 responds with an acknowledge.
At this time the data is written only to volatile registers, then the device enters its standby state.
Table 3. WCR Write Operation
1st byte
2nd byte
3rd byte
AR address - 02h
WCR(80h) selection
ST 0 1 0 1 0 0 0 0 A 0 0 0 0 0 0 1 0 A 1 0 0 0 0 0 0 0 A SP
slave address byte
WCR address - 00h
data byte
ST 0 1 0 1 0 0 0 0 A 0 0 0 0 0 0 0 0 A X X X X X X X X A SP
An increment operation (see Table 4) requires a Start condition, followed by a valid increment address byte (01011),
a valid address byte 00h. After each of the two bytes, the CAT5132 responds with an acknowledge. At this time if the
data is high then the wiper is incremented or if the data is low the wiper is decremented at each clock. Once the stop
is issued then the device enters its standby state with the WCR data as being the last inc/dec position. Also, the wiper
position does not roll over but is limited to min and max positions.
Table 4. WCR Increment/Decrement Operation
ST 0
1st byte
10 10 0 0
2nd byte
AR address - 02h
0A0 000 0 0
3rd byte
WCR(80h) selection
1 0 A 1 0 0 0 0 0 0 0 A SP
slave address byte
WCR address - 00h
increment (1) / decrement (0) bits
ST 0 1 0 1 1 0 0 0 A 0 0 0 0 0 0 0 0 A 1 1 1 1 0 0 0 0
SP
A read operation (see Table 5) requires a Start condition, followed by a valid slave address byte for write, a valid address
byte 00h, a second START and a second slave address byte for read. After each of the three bytes, the CAT5132
responds with an acknowledge and then the device transmits the data byte. The master terminates the read operation
by issuing a STOP condition following the last bit of Data byte.
Table 5. WCR Read Operation
1st byte
2nd byte
3rd byte
AR address - 02h
WCR(80h) selection
ST 0 1 0 1 0 0 0 0 A 0 0 0 0 0 0 1 0 A 1 0 0 0 0 0 0 0 A SP
slave address byte
WCR address - 00h
ST 0 1 0 1 0 0 0 0 A 0 0 0 0 0 0 0 0
slave address byte
data byte
ST 0 1 0 1 0 0 0 1 A 0 X X X X X X X
SP
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice.
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Doc No. MD-2124, Rev. F