CAT5132ZI-10-GT3 Datasheet, PDF (7/14 Pages) ON Semiconductor – 16 Volt Digitally Programmable Potentiometer with 128 Taps and I2C Interface

CAT5132
SERIAL BUS PROTOCOL
The following defines the features of the I²C bus
protocol:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock is high will be
interpreted as a START or STOP condition.
The device controlling the transfer is a master, typically
a processor or controller, and the device being controlled
is the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the CAT5132 will be considered
a slave device in all applications.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT5132 monitors the
SDA and SCL lines and will not respond until this
condition is met (see Fig. 3).
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition (see Fig. 3).
Acknowledge
After a successful data transfer, each receiving device
is required to generate an acknowledge. The
acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data (see Fig. 4).
The CAT5132 responds with an acknowledge after
receiving a START condition and its slave address. If
the device has been selected along with a write operation,
it responds with an acknowledge after receiving each
8-bit byte.
When the CAT5132 is in a READ mode it transmits 8 bits
of data, releases the SDA line, and monitors the line for
an acknowledge. Once it receives this acknowledge,
the CAT5132 will continue to transmit data. If no
acknowledge is sent by the Master, the device terminates
data transmission and waits for a STOP condition.
Acknowledge Polling
The disabling of the inputs can be used to take advantage
of the typical write cycle time. Once the STOP condition
is issued to indicate the end of the write operation, the
CAT5132 initiates the internal write cycle. ACK polling
can be initiated immediately. This involves issuing the
START condition followed by the slave address. If the
CAT5132 is still busy with the write operation, no ACK
will be returned. If the CAT5132 has completed the write
operation, an ACK will be returned and the host can then
proceed with the next instruction operation.
SCL
SDA
START
CONDITION
Figure 3. Start/Stop Condition
STOP
CONDITION
SCL FROM
MASTER
BUS RELEASE DELAY (TRANSMITTER)
1
8
BUS RELEASE DELAY (RECEIVER)
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACK DELAY (≤ tAA)
ACK SETUP (≥ tSU:DAT)
Figure 4. Acknowledge Condition
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice.
7
Doc No. MD-2124, Rev. F