CAT5132ZI-10-GT3 Datasheet, PDF (8/14 Pages) ON Semiconductor – 16 Volt Digitally Programmable Potentiometer with 128 Taps and I2C Interface

CAT5132
DEVICE DESCRIPTION
Access Control Register
The volatile register WCR and the non-volatile register
DR are accessed only by addressing the volatile Access
Register AR first, using the 3 byte I²C protocol for all read
and write operations (see Table 1). The first byte is the
slave address/instruction byte (see details below). The
second byte contains the address (02h) of the AR
register. The data in the third byte controls which register
WCR (80h) or DR (00h) is being addressed (see Figure
5).
Slave Address Instruction Byte Description
The first byte sent to the CAT5132 from the master
processor is called the Slave/DPP Address Byte. The
most significant five bits of the slave address are a
device type identifier. For the CAT5132 these bits are
fixed at 01010 (refer to Table 2).
The next two bits, A1 and A0, are the internal slave
address and must match the physical device address
which is defined by the state of the A1 and A0 input pins.
Only the device with slave address matching the input
byte will be accessed by the master. This allows up to 4
devices to reside on the same bus. The A1 and A0 inputs
can be actively driven by CMOS input signals or tied to
V_CC or Ground.
The last bit is the READ/WRITE bit and determines the
function to be performed. If it is a “1” a read command is
initiated and if it is a “0” a write is initiated. For the AR
register only write is allowed.
After the Master sends a START condition and the slave
address byte, the CAT5132 monitors the bus and
responds with an acknowledge when its address matches
the transmitted slave address.
Table 1. Access Control Register
ST 0
ST 0
1st byte
10 10 0 0
10 10 0 0
2nd byte
3rd byte
AR address - 02h
WCR(80h) / DR (00h) selection
0 A 0 0 0 0 0 0 1 0 A 1 0 0 0 0 0 0 0 A SP
0 A 0 0 0 0 0 0 1 0 A 0 0 0 0 0 0 0 0 A SP
Table 2. Byte 1 Slave Address and Instruction Byte
Device Type Identifier
ID4
ID3
ID2
ID1
ID0
0
1
0
1
0
(MSB)
Slave Address
A1
A0
X
X
Read/Write
R/W
X
(LSB)
BUS ACTIVITY:
MASTER
SLAVE
S ^ADDRESS
T ^{& INSTRUCTION}
A
R
T ^FIXED
SDA LINE S
VARIABLE A
C
K
AR REGISTER WCR/DR
ADDRESS SELECTION
S
T
O
P
P
A
A
C
C
K
K
Figure 5. Access Register Addressing Using 3 Bytes
Doc. No. MD-2124, Rev. F
© 2008 SCILLC. All rights reserved.
8
Characteristics subject to change without notice.