CAT28LV64 Datasheet, PDF (9/15 Pages) Catalyst Semiconductor – 64K-Bit CMOS PARALLEL E2PROM

CAT28LV64
Hardware Data Protection
The following is a list of hardware data protection features
that are incorporated into the CAT28LV64.
1. V_CC sense provides for write protection when V_CC
falls below 2.0 V min.
2. A power on delay mechanism, t_INIT (see AC
characteristics), provides a 5 to 10 ms delay before
a write sequence, after V_CC has reached 2.40 V
min.
3. Write inhibit is activated by holding any one of
OE low, CE high or WE high.
4. Noise pulses of less than 20 ns on the WE or CE
inputs will not result in a write cycle.
Software Data Protection
The CAT28LV64 features a software controlled data
protection scheme which, once enabled, requires a data
algorithm to be issued to the device before a write can be
performed. The device is shipped from ON Semiconductor
with the software protection NOT ENABLED (the
CAT28LV64 is in the standard operating mode).
WRITE DATA:
ADDRESS:
AA
1555
WRITE DATA:
ADDRESS:
AA
1555
WRITE DATA:
ADDRESS:
55
0AAA
WRITE DATA:
ADDRESS:
55
0AAA
WRITE DATA:
ADDRESS:
A0
1555
WRITE DATA:
ADDRESS:
80
1555
SOFTWARE DATA
PROTECTION ACTIVATED (Note 14)
WRITE DATA:
ADDRESS:
AA
1555
WRITE DATA: XX
TO ANY ADDRESS
WRITE DATA:
ADDRESS:
55
0AAA
WRITE LAST BYTE
TO
LAST ADDRESS
WRITE DATA:
ADDRESS:
20
1555
Figure 10. Write Sequence for Activating Software
Data Protection
Figure 11. Write Sequence for Deactivating
Software Data Protection
14. Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within t_BLC Max.,
after SDP activation.
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