CAT28LV64 Datasheet, PDF (3/15 Pages) Catalyst Semiconductor – 64K-Bit CMOS PARALLEL E2PROM

CAT28LV64
A₅−A₁₂
V_CC
CE
OE
WE
A₀−A₄
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
CONTROL
LOGIC
TIMER
ADDR. BUFFER
& LATCHES
ROW
DECODER
HIGH VOLTAGE
GENERATOR
DATA POLLING
AND
TOGGLE BIT
COLUMN
DECODER
8,192 x 8
E²PROM
ARRAY
32 BYTE PAGE
REGISTER
I/O BUFFERS
I/O₀−I/O₇
Figure 1. Block Diagram
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
Temperature Under Bias
−55 to +125
°C
Storage Temperature
−65 to +150
°C
Voltage on Any Pin with Respect to Ground (Note 1)
V_CC with Respect to Ground
Package Power Dissipation Capability (T_A = 25°C)
Lead Soldering Temperature (10 secs)
−2.0 V to +V_CC + 2.0 V
V
−2.0 to +7.0
V
1.0
W
300
°C
Output Short Circuit Current (Note 2)
100
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The minimum DC input voltage is −0.5 V. During transitions, inputs may undershoot to −2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is V_CC + 0.5 V, which may overshoot to V_CC + 2.0 V for periods of less than 20 ns.
2. Output shorted for no more than one second. No more than one output shorted at a time.
Table 2. RELIABILITY CHARACTERISTICS (Note 3)
Symbol
Parameter
Test Method
Min
Max
N_END
Endurance
MIL−STD−883, Test Method 1033
10⁵
T_DR
Data Retention
MIL−STD−883, Test Method 1008
100
V_ZAP
ESD Susceptibility
MIL−STD−883, Test Method 3015
2,000
I_LTH (Note 4)
Latch−Up
JEDEC Standard 17
100
3. These parameters are tested initially and after a design or process change that affects the parameters.
4. Latch−up protection is provided for stresses up to 100 mA on address and data pins from −1 V to V_CC + 1 V.
Table 3. MODE SELECTION
Mode
CE
WE
OE
I/O
Read
L
H
L
D_OUT
Byte Write (WE Controlled)
L
H
D_IN
Units
Cycles/Byte
Years
V
mA
Power
ACTIVE
ACTIVE
Byte Write (CE Controlled)
L
H
D_IN
ACTIVE
Standby and Write Inhibit
H
X
X
High−Z
STANDBY
Read and Write Inhibit
X
H
H
High−Z
ACTIVE
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