CAT25512VI-GT3 Datasheet, PDF (9/16 Pages) ON Semiconductor – 512-Kb SPI Serial CMOS EEPROM

CAT25512
READ OPERATIONS
Read from Memory Array
To read from memory, the host sends a READ instruction
followed by a 16−bit address.
After receiving the last address bit, the CAT25512 will
respond by shifting out data on the SO pin (as shown in
Figure 9). Sequentially stored data can be read out by simply
continuing to run the clock. The internal address pointer is
automatically incremented to the next higher address as data
is shifted out. After reaching the highest memory address,
the address counter “rolls over” to the lowest memory
address, and the read cycle can be continued indefinitely.
The read operation is terminated by taking CS high.
Read Identification Page
Reading the additional 128−byte Identification Page (IP)
is achieved using the same Read command sequence as used
for Read from main memory array (Figure 9). The IPL bit
from the Status Register must be set (IPL = 1) before
attempting to read from the IP. The [A6:A0] are the address
significant bits that point to the data byte shifted out on the
SO pin. If the CS continues to be held low, the internal
address register defined by [A6:A0] bits is automatically
incremented and the next data byte from the IP is shifted out.
The byte address must not exceed the 128−byte page
boundary.
Read Status Register
To read the status register, the host simply sends a RDSR
command. After receiving the last bit of the command, the
CAT25512 will shift out the contents of the status register on
the SO pin (Figure 10). The status register may be read at
any time, including during an internal write cycle.
While the internal write cycle is in progress, the RDSR
command will output the full content of the status register.
For easy detection of the internal write cycle completion,
during writing to the memory array we recommend
sampling the RDY bit only through the polling routine.
After detecting the RDY bit “0”, the next RDSR instruction
will always output the expected content of the status register.
Note: During writing to the status register (WRSR) we
recommend to avoid the polling routine and do insert a
fixed delay of 5 ms to allow the internal write cycle to
complete.
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30
OPCODE
BYTE ADDRESS*
SI
0 0 0 0 0 0 1 1 ^AN
A₀
HIGH IMPEDANCE
SO
Dashed Line = mode (1, 1)
* Please check the Byte Address Table (Table 11)
76
MSB
DATA OUT
54 3 2
10
Figure 9. READ Timing
CS
SCK
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14
OPCODE
SI
0
0
0
0
0
1
01
HIGH IMPEDANCE
SO
DATA OUT
7
6
5
4
32
10
Dashed Line = mode (1, 1)
MSB
Figure 10. RDSR Timing
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