CAT25512VI-GT3 Datasheet, PDF (8/16 Pages) ON Semiconductor – 512-Kb SPI Serial CMOS EEPROM

CAT25512
Write Status Register
The Status Register is written by sending a WRSR
instruction according to timing shown in Figure 7. Only bits
2, 3, 4, 6 and 7 can be written using the WRSR command.
The internal programming for the SR bits will start after
the low to high CS transition. The internal write cycle will
last maximum 5 ms (t_WC).
It is recommended to avoid SR polling routine (through
RDSR) while writing to the status register is in progress
and insert a fixed delay of 5 ms before sending any other
instruction to the CAT25512.
Write Protection
The Write Protect (WP) pin can be used to protect the
Block Protect bits BP0 and BP1 against being inadvertently
altered. When WP is low and the WPEN bit is set to “1”,
write operations to the Status Register are inhibited. WP
going low while CS is still low will interrupt a write to the
status register. If the internal write cycle has already been
initiated, WP going low will have no effect on any write
operation to the Status Register. The WP pin function is
blocked when the WPEN bit is set to “0”. The WP input
timing is shown in Figure 8.
CS
SCK
01
2
3
4
5
6
78
9 10 11 12 13 14 15
OPCODE
SI
0
0
0
0
00
SO
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
0
1
7
6
5
MSB
Figure 7. WRSR Timing
DATA IN
4 32
10
t_WPS
t_WPH
CS
SCK
WP
WP
Dashed Line = mode (1, 1)
Figure 8. WP Timing
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