CAT9555 Datasheet, PDF (8/18 Pages) Catalyst Semiconductor – 16-bit I2C and SMBus I/O Port with Interrupt

CAT9555
¯IN¯T¯: Interrupt Output
The open-drain interrupt output is activated when one of
the port pins configured as an input changes state
(differs from the corresponding input port register bit
state). The interrupt is deactivated when the input returns
to its previous state or the input port register is read.
Since there are two 8-bit ports that are read
independently, the interrupt caused by Port 0 will not
be cleared by a read of Port 1, or vice versa.
Changing an I/O from an output to an input may cause
a false interrupt if the state of the pin does not match
the contents of the input port register.
Data from
Shift Register
Data from
Shift Register
Write
Configuration Pulse
Configuration
Register
D
Q
FF
CK
Q
Write Pulse
Read Pulse
Data from
Shift Register
Write
Polarity
Register
D
Q
FF
CK
Q
Output Port
Register
Q1
Input Port
Register
D
Q
LATCH
CK
Q
D
Q
FF
CK
Q
Polarity
Inversion Register
Figure 4. Simplified Schematic of I/Os
100kΩ
Q2
Output Port
Register Data
VCC
I/O Pin
VSS
Input Port
Register Data
To INT
Polarity
Register Data
Doc. No. MD-9003 Rev. J
8
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Characteristics subject to change without notice