CAT9555 Datasheet, PDF (1/18 Pages) Catalyst Semiconductor – 16-bit I2C and SMBus I/O Port with Interrupt

CAT9555
16-bit I²C and SMBus I/O Port with Interrupt
FEATURES
„ 400kHz I²C bus compatible
„ 2.3V to 5.5V operation
„ Low stand-by current
„ 5V tolerant I/Os
„ 16 I/O pins that default to inputs at power-up
„ High drive capability
„ Individual I/O configuration
„ Polarity inversion register
„ Active low interrupt output
„ Internal power-on reset
„ No glitch on power-up
„ Noise filter on SDA/SCL inputs
„ Cascadable up to 8 devices
„ Industrial temperature range
„ RoHS-compliant 24-lead SOIC and TSSOP, and
24-pad TQFN (4 x 4mm) packages
APPLICATIONS
„ White goods (dishwashers, washing machines)
„ Handheld devices (cell phones, PDAs, digital
cameras)
„ Data Communications (routers, hubs and servers)
BLOCK DIAGRAM ⁽¹⁾
DESCRIPTION
The CAT9555 is a CMOS device that provides 16-bit
parallel input/output port expansion for I²C and SMBus
compatible applications. These I/O expanders provide
a simple solution in applications where additional I/Os
are needed: sensors, power switches, LEDs,
pushbuttons, and fans.
The CAT9555 consists of two 8-bit Configuration ports
(input or output), Input, Output and Polarity inversion
registers, and an I²C/SMBus-compatible serial interface.
Any of the sixteen I/Os can be configured as an input
or output by writing to the configuration register. The
system master can invert the CAT9555 input data by
writing to the active-high polarity inversion register.
The CAT9555 features an active low interrupt output
which indicates to the system master that an input
state has changed.
The three address input pins provide the device's
extended addressing capability and allow up to eight
devices to share the same bus. The fixed part of the
I²C slave address is the same as the CAT9554,
allowing up to eight of these devices in any
combination to be connected on the same bus.
For Ordering Information details, see page 17.
A0
A1
A2
SCL
SDA
V_CC
V_SS
INPUT
FILTER
POWER-ON
RESET
8-BIT
WRITE pulse
READ pulse
INPUT/
OUTPUT
PORTS
I²C/SMBUS
CONTROL
8-BIT
WRITE pulse
READ pulse
INPUT/
OUTPUT
PORTS
LP FILTER
I/O_1.0
I/O_1.1
I/O_1.2
I/O_1.3
I/O_1.4
I/O_1.5
I/O_1.6
I/O_1.7
I/O_0.0
I/O_0.1
I/O_0.2
I/O_0.3
I/O_0.4
I/O_0.5
I/O_0.6
I/O_0.7
V_INT
INT
Notes:
(1) All I/Os are set to inputs at RESET
© 2010 SCILLC. All rights reserved
1
Characteristics subject to change without notice
Doc. No. MD-9003, Rev. J