CAT9532 Datasheet, PDF (8/18 Pages) ON Semiconductor – 16-bit Programmable LED Dimmer with I2C Interface

CAT9532
Acknowledge
After a successful data transfer, each receiving device
is required to generate an acknowledge. The
acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8
bits of data. The SDA line remains stable LOW during
the HIGH period of the acknowledge related clock
pulse (Figure 4).
The CAT9532 responds with an acknowledge after
receiving a START condition and its slave address. If
the device has been selected along with a write
operation, it responds with an acknowledge after
receiving each 8- bit byte.
When the CAT9532 begins a READ mode it transmits
8 bits of data, releases the SDA line, and monitors the
line for an acknowledge. Once it receives this
acknowledge, the CAT9532 will continue to transmit
data. If no acknowledge is sent by the Master, the
device terminates data transmission and waits for a
STOP condition. The master must then issue a stop
condition to return the CAT9532 to the standby power
mode and place the device in a known state.
Registers and Bus Transactions
After the successful acknowledgement of the slave
address, the bus master will send a command byte to
the CAT9532 which will be stored in the Control
Register. The format of the Control Register is shown
in Figure 5.
The Control Register acts as a pointer to determine
which register will be written or read. The four least
significant bits, B0, B1, B2, B3, are used to select
which internal register is accessed, according
to the Table 1.
If the auto increment flag (AI) is set, the four least
significant bits of the Control Register are
automatically incremented after a read or write
operation. This allows the user to access the
CAT9532 internal registers sequentially. The content
of these bits will rollover to “0000” after the last
register is accessed.
Table 1. Internal Registers Selection
Register
B3 B2 B1 B0 Name
Type
Register
Function
0
0
0
0
INPUT0 READ
Input
Register 0
0
0
0
1
INPUT1 READ
Input
Register 1
0 0 1 0 PSC0
READ/ Frequency
WRITE Prescaler 0
00
11
PW M0
READ/ PWM
WRITE Register 0
0 1 0 0 PSC1
READ/ Frequency
WRITE Prescaler 1
01
01
PW M1
READ/ PWM
WRITE Register 1
0 1 1 0 LS0
READ/ LED 0-3
WRITE Selector
0 1 1 1 LS1
READ/ LED 4-7
WRITE Selector
1 0 0 0 LS2
READ/ LED 8-11
WRITE Selector
1 0 0 1 LS3
READ/ LED 12-15
WRITE Selector
Figure 4. Acknowledge Timing
SCL FROM
1
MASTER
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 5. Control Register
0 0 0 AI B3 B2 B1 B0
REGISTER ADDRESS
RESET STATE: 00h _{AUTO-INCREMENT FLAG}
Doc. No. MD-9001 Rev. E
8
© 2010 SCILLC. All rights reserved
Characteristics subject to change without notice