CAT9532 Datasheet, PDF (10/18 Pages) ON Semiconductor – 16-bit Programmable LED Dimmer with I2C Interface

CAT9532
Write Operations
Data is transmitted to the CAT9532 registers using the
write sequence shown in Figure 6.
If the AI bit from the command byte is set to “1”, the
CAT9532 internal registers can be written
sequentially. After sending data to one register, the
next data byte will be sent to the next register
sequentially addressed.
Read Operations
The CAT9532 registers are read according to the
timing diagrams shown in Figure 7 and Figure 8. Data
from the register, defined by the command byte, will
be sent serially on the SDA line.
After the first byte is read, additional data bytes may
be read when the auto-increment flag, AI, is set. The
additional data byte will reflect the data read from the
next register sequentially addressed by the (B3 B2 B1
B0) bits of the command byte.
When reading Input Port Registers (Figure 8), data is
clocked into the register on the failing edge of the
acknowledge clock pulse. The transfer is stopped
when the master will not acknowledge the data byte
received and issue the STOP condition.
Figure 6. Write to Register Timing Diagram
LED Pins Used as General Purpose I/O
Any LED pins not used to drive LEDs can be used as
general purpose input/output, GPIO.
When used as input, the user should program the
corresponding LED pin to Hi-Z (“00” for the LSx
register bits). The pin state can be read via the
Input Register according to the sequence shown in
Figure 8.
For use as output, an external pull-up resistor should
be connected to the pin. The value of the pull-up
resistor is calculated according to the DC operating
characteristics. To set the LED output high, the user
has to program the output Hi-Z writing “00” into the
corresponding LED Selector (LSx) register bits. The
output pin is set low when the LED output is
programmed low through the LSx register bits (“01” in
LSx register bits).
1 23 456 78 9
SCL
Slave Address
Command Byte
Data To Register 1
Data To Register 2
SDA S 1 1 0 0 A2 A1 A0 0 A 0 0 0 AI B3 B2 B1 B0 A
DATA 1
Start Condition
R/W Acknowledge
From Slave
Acknowledge
From Slave
WRITE TO
REGISTER
A
Acknowledge
From Slave
1.0 A
DATA OUT
FROM PORT
Figure 7. Read from Register Timing Diagram
Slave Address
Acknowledge
From Slave
Acknowledge
From Slave
t_pv
Slave Address
Acknowledge
Acknowledge
From Slave
From Master
Data From Register
S 1 1 0 0 A2 A1 A0 0 A
R/W
COMMAND BYTE
A S 1 1 0 0 A2 A1 A0 1 A MSB
DATA
LSB A
At This Moment Master-Transmitter
Becomes Master-receiver and
Slave-Receiver Becomes
Slave-Transmitter
R/W
First Byte
Auto-increment
Register Address
If Al = 1
No Acknowledge
Data From Register From Master
Note: Transfer can be stopped at any time by a STOP condition.
MSB
DATA
Last Byte
LSB NA P
Doc. No. MD-9001 Rev. E
10
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Characteristics subject to change without notice