CAT93C56LI-G Datasheet, PDF (8/17 Pages) ON Semiconductor – 2-Kb Microwire Serial CMOS EEPROM

CAT93C56, CAT93C57
Write
After receiving a WRITE command (Figure 5), address
and the data, the CS (Chip Select) pin must be deselected for
a minimum of t_CSMIN. The falling edge of CS will start the
self clocking clear and data store cycle of the memory
location specified in the instruction. The clocking of the SK
pin is not necessary after the device has entered the self
clocking mode. The ready/busy status of the CAT93C56/57
can be determined by selecting the device and polling the
DO pin. Since this device features Auto−Clear before write,
it is NOT necessary to erase a memory location before it is
written into.
Erase
Upon receiving an ERASE command and address, the CS
(Chip Select) pin must be deasserted for a minimum of
t_CSMIN (Figure 6). The falling edge of CS will start the self
clocking clear cycle of the selected memory location. The
clocking of the SaK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAT93C56/57 can be determined by selecting the device
and polling the DO pin. Once cleared, the content of a
cleared location returns to a logical “1” state.
SK
CS
A_N A_N−1
DI
101
A₀ D_N
D₀
t_CSMIN
STATUS
VERIFY
STANDBY
t_SV
BUSY
t_HZ
HIGH−Z
DO
READY
HIGH−Z
t_EW
Figure 5. Write Instruction Timing
SK
CS
A_N A_N−1
A₀
DI
11 1
STATUS VERIFY
t_CS
STANDBY
t_SV
t_HZ
HIGH−Z
DO
BUSY READY
HIGH−Z
t_EW
Figure 6. Erase Instruction Timing
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