CAT93C56LI-G Datasheet, PDF (4/17 Pages) ON Semiconductor – 2-Kb Microwire Serial CMOS EEPROM

CAT93C56, CAT93C57
Table 6. A.C. CHARACTERISTICS (Note 5), CAT93C56, Die Rev. G – New Product
(V_CC = +1.8V to +5.5V, T_A = −40°C to +125°C, unless otherwise specified.)
Limits
Symbol
Parameter
Min
t_CSS
t_CSH
t_DIS
t_DIH
t_PD1
t_PD0
t_HZ (Note 6)
t_EW
t_CSMIN
t_SKHI
t_SKLOW
t_SV
SK_MAX
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High−Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
50
0
100
100
0.25
0.25
0.25
DC
Max
0.25
0.25
100
5
0.25
2000
Units
ns
ns
ns
ns
ms
ms
ns
ms
ms
ms
ms
ms
kHz
Table 7. A.C. CHARACTERISTICS (Note 5), CAT93C56/57, Die Rev. E – Mature Product
(CAT93C56 Rev. E − NOT RECOMMENDED FOR NEW DESIGNS)
Limits
Symbol
t_CSS
t_CSH
t_DIS
t_DIH
t_PD1
t_PD0
t_HZ
(Note 6)
Parameter
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High−Z
V_CC = 1.8 V − 5.5 V
Min
Max
200
0
400
400
1
1
400
V_CC = 2.5 V − 5.5 V
Min
Max
100
0
200
200
0.5
0.5
200
V_CC = 4.5 V − 5.5 V
Min
Max
50
0
100
100
0.25
0.25
100
t_EW
Program/Erase Pulse Width
10
10
10
t_CSMIN
Minimum CS Low Time
1
0.5
0.25
t_SKHI
Minimum SK High Time
1
0.5
0.25
t_SKLOW
Minimum SK Low Time
1
0.5
0.25
t_SV
Output Delay to Status Valid
1
0.5
0.25
SK_MAX
Maximum Clock Frequency
DC
250
DC
500
DC
1000
Units
ns
ns
ns
ns
ms
ms
ns
ms
ms
ms
ms
ms
kHz
Table 8. POWER−UP TIMING (Notes 6 and 7)
Symbol
Parameter
Max
Units
t_PUR
Power−up to Read Operation
1
ms
t_PUW
Power−up to Write Operation
1
ms
5. Test conditions according to “A.C. Test Conditions” table.
6. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate
AEC−Q100 and JEDEC test methods.
7. t_PUR and t_PUW are the delays required from the time V_CC is stable until the specified operation can be initiated.
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