CAT5409_13 Datasheet, PDF (8/15 Pages) ON Semiconductor – Quad Digital Potentiometer (POT)

CAT5409
WRITE OPERATIONS
In the Write mode, the Master device sends the START
condition and the slave address information to the Slave
device. After the Slave generates an acknowledge, the
Master sends the instruction byte that defines the requested
operation of CAT5409. The instruction byte consist of a
four-bit opcode followed by two register selection bits and
two pot selection bits. After receiving another acknowledge
from the Slave, the Master device transmits the data to be
written into the selected register. The CAT5409
acknowledges once more and the Master generates the
STOP condition, at which time if a non-volatile data register
is being selected, the device begins an internal programming
cycle to non-volatile memory. While this internal cycle is in
progress, the device will not respond to any request from the
Master device.
Acknowledge Polling
The disabling of the inputs can be used to take advantage
of the typical write cycle time. Once the stop condition is
issued to indicate the end of the host’s write operation, the
CAT5409 initiates the internal write cycle. ACK polling can
be initiated immediately. This involves issuing the start
condition followed by the slave address. If the CAT5409 is
still busy with the write operation, no ACK will be returned.
If the CAT5409 has completed the write operation, an ACK
will be returned and the host can then proceed with the next
instruction operation.
Write Protection
The Write Protection feature allows the user to protect
against inadvertent programming of the non-volatile data
registers. If the WP pin is tied to LOW, the data registers are
protected and become read only. Similarly, the WP pin going
low after start but after start will interrupt non−volatile write
to data registers, while the WP pin going low after internal
write cycle has started, will have no effect on any write
operation. The CAT5409 will accept both slave addresses
and instructions, but the data registers are protected from
programming by the device’s failure to send an
acknowledge after data is received.
CAT5409 0 1 0 1 A3 A2 A1 A0
* A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device.
** A0, A1, A2 and A3 must compare to its corresponding hard wired input pins.
Figure 6. Slave Address Bits
INSTRUCTION
BYTE
S
T
BUS ACTIVITY: ^A
SLAVE
ADDRESS
MASTER
R
T
Fixed
Variable
S
T
DR1 WCRDATA
O
P
SDA LINE S
P
A
A
A
C
C
C
K
K
K
Figure 7. Write Timing
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