CAT5409_13 Datasheet, PDF (5/15 Pages) ON Semiconductor – Quad Digital Potentiometer (POT)

CAT5409
Table 5. D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Test Conditions
Min
Max
I_CC
I_SB
I_LI
I_LO
V_IL
V_IH
V_OL1
Power Supply Current
Standby Current (V_CC = 5 V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage (V_CC = 3 V)
f_SCL = 400 kHz
V_IN = GND or V_CC, SDA Open
V_IN = GND to V_CC
V_OUT = GND to V_CC
I_OL = 3 mA
−1
V_CC x 0.7
1
1
10
10
V_CC x 0.3
V_CC + 1.0
0.4
Units
mA
mA
mA
mA
V
V
V
Table 6. CAPACITANCE (Note 8) (T_A = 25C, f = 1.0 MHz, V_CC = 5 V)
Symbol
Test
Conditions
C_I/O
Input/Output Capacitance (SDA)
V_I/O = 0 V
C_IN
Input Capacitance (A0, A1, A2, A3, SCL, WP)
V_IN = 0 V
8. This parameter is tested initially and after a design or process change that affects the parameter.
Table 7. A.C. CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Min
Typ
f_SCL
Clock Frequency
T_I (Note 10)
Noise Suppression Time Constant at SCL, SDA Inputs
t_AA
SLC Low to SDA Data Out and ACK Out
t_BUF (Note 10)
Time the bus must be free before a new transmission can start
1.2
t_HD:STA
Start Condition Hold Time
0.6
t_LOW
Clock Low Period
1.2
t_HIGH
Clock High Period
0.6
t_SU:STA
Start Condition SetupTime (for a Repeated Start Condition)
0.6
t_HD:DAT
Data in Hold Time
0
t_SU:DAT
Data in Setup Time
100
t_R (Note 10)
SDA and SCL Rise Time
t_F (Note 10)
SDA and SCL Fall Time
t_SU:STO
Stop Condition Setup Time
0.6
t_DH
Data Out Hold Time
50
Max
8
6
Max
400
50
0.9
0.3
300
Units
pF
pF
Units
kHz
ns
ms
ms
ms
ms
ms
ms
ns
ns
ms
ns
ms
ns
Table 8. POWER UP TIMING (Note 10)
Symbol
t_PUR
t_PUW
Power-up to Read Operation
Power-up to Write Operation
Parameter
Max
Units
1
ms
1
ms
Table 9. WRITE CYCLE LIMITS (Note 9)
Symbol
Parameter
Max
Units
t_WR
Write Cycle Time
5
ms
9. The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write
cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
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