CAT5273 Datasheet, PDF (8/14 Pages) ON Semiconductor – Dual 256‐position I2C Compatible Digital Potentiometers (POTs)

CAT5271, CAT5273
Table 9. CODES AND CORRESPONDING R_WA
RESISTANCE FOR R_AB = 100 kW, V_DD = 5 V
D (Dec.) R_WA (W)
Output State
255
441
Full Scale
128
50,050 Midscale
1
99,659 1 LSB
0
100,050 Zero Scale
Typical device to device resistance matching is lot
dependent and may vary by up to 20%.
ESD Protection
Digital
Input
LOGIC
GND
W, A, B
Potentiometer
GND
Figure 15. ESD Protection Networks
Terminal Voltage Operating Range
The CAT5271/CAT5273 V_DD and GND power supply
define the limits for proper 3-terminal digital potentiometer
operation. Signals or potentials applied to terminals A, B or
the wiper must remain inside the span of V_DD and GND.
Signals which attempt to go outside these boundaries will be
clamped by the internal forward biased diodes.
V_DD
W, A, B
LOGIC
CAT5271
GND
Figure 16.
Power-up Sequence
Because ESD protection diodes limit the voltage
compliance at terminals A, B, and W (see Figure 15), it is
recommended that V_DD/GND be powered before applying
any voltage to terminals A, B, and W. The ideal power-up
sequence is: GND, V_DD, digital inputs, and then V_A/B/W. The
order of powering V_A, V_B, V_W, and the digital inputs is not
important as long as they are powered after V_DD/GND.
Power Supply Bypassing
Good design practice employs compact, minimum lead
length layout design. Leads should be as direct as possible.
It is also recommended to bypass the power supplies with
quality low ESR Ceramic chip capacitors of 0.01 mF to
0.1 mF. Low ESR 1 mF to 10 mF tantalum or electrolytic
capacitors can also be applied at the supplies to suppress
transient disturbances and low frequency ripple. As a further
precaution digital ground should be joined remotely to the
analog ground at one point to minimize the ground bounce.
V_DD
+
C₃
10 mF
C₁
0.1 mF
V_DD
CAT5271
GND
Figure 17. Power Supply Bypassing
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