CAT5273 Datasheet, PDF (4/14 Pages) ON Semiconductor – Dual 256‐position I2C Compatible Digital Potentiometers (POTs)

CAT5271, CAT5273
Table 4. CAPACITANCE
T_A = 25C, f = 1.0 MHz, V_DD = 5 V
Symbol
Test
C_I/O
Input/Output Capacitance (SDA, SCL)
(Note 11)
Conditions
V_I/O = 0 V
Table 5. POWER UP TIMING (Notes 11 and 12)
Symbol
Parameter
t_PUR
Power-up to Read Operation
t_PUW
Power-up to Write Operation
11. This parameter is tested initially and after a design or process change that affects the parameter.
12. t_PUR and t _PUW are delays required from the time V_CC is stable until the specified operation can be initiated.
Table 6. DIGITAL POTENTIOMETER TIMING
Symbol
Parameter
Min
t_WRPO
t_WR
Wiper Response Time After Power Supply Stable
Wiper Response Time: SCL falling edge after last bit of wiper position data byte to
wiper change
Table 7. A.C. CHARACTERISTICS
V_DD = +2.7 V to +5.5 V, −40C to +85C unless otherwise specified.
Symbol
Parameter
f_SCL
t_HIGH
t_LOW
t_SU:STA
t_HD:STA
t_SU:DAT
t_HD:DAT
t_SU:STO
t_BUF
t_R
t_F
t_DH
T_I
t_AA
Clock Frequency
Clock High Period
Clock Low Period
Start Condition Setup Time (for a Repeated Start Condition)
Start Condition Hold Time
Data in Setup Time
Data in Hold Time
Stop Condition Setup Time
Time the bus must be free before a new transmission can start
SDA and SCL Rise Time
SDA and SCL Fall Time
Data Out Hold Time
Noise Suppression Time Constant at SCL, SDA Inputs
SCL Low to SDA Data Out and ACK Out
Min
Typ
600
1300
600
600
100
0
600
1300
100
Max
Units
8
pF
Max
Units
1
ms
1
ms
Max
Units
50
ms
20
ms
Max
Units
400
kHz
ns
ns
ns
ns
ns
ns
ns
ns
300
ns
300
ns
ns
50
ns
1
ms
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