CAT5140 Datasheet, PDF (8/11 Pages) ON Semiconductor – Single Channel 256 Tap DPP with Integrated EEPROM and I2C Control

CAT5140
Address 1: Device ID (Read Only)
Bit 7 defines the DPP device manufacturer; Catalyst/On Semiconductor = high (1)
Bit
7
6
5
4
3
2
1
0
Name
1
1
0
1
0
0
0
0
A writing to address 1 has no effect. Attempts to do so will return an ACK but no data will be written.
Address 0: IVR/WR Register (I/O)
Address 00h accesses one of two memory registers: the initial value register (IVR) or the wiper register (WR) depending
upon the value of bit 7 in Access Control Register (ACR) which is at address 08h, above.
WR controls the wiper’s position and is a volatile memory while IVR is non−volatile and retains its data after the chip has
been powered down. Writes to IVR automatically update the WR while writes to WR leave IVR unaffected.
WR: Wiper Register = Volatile.
IVR: Initial Value Register = Non−volatile.
Writing and Reading operations:
1. If Bit 7 from ACR is 0 (non−volatile):
♦ A write operation to address 00h will write the same value in WR and IVR.
♦ A read operation to address 00h will output the content of IVR.
2. If bit 7 from ACR is 1 (volatile):
♦ A write operation to address 00h will write in WR only.
♦ A read operation to address 00h will output the content of WR.
All changes to the wiper’s position are immediate. There is no delay the wiper’s movement when writing to non−volatile
memory.
Bit
7
6
5
4
3
2
1
0
Name
−
−
−
−
−
−
−
−
IVR is preprogrammed at the factory to a default value of “80h”.
I²C SERIAL BUS INSTRUCTION FORMAT
Table 14. I²C SLAVE ADDRESS BITS
Slave Address
Transfer Data
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1
Read
51h
0
1
0
1
0
0
0
Write
50h
If the Slave Address Byte sent by the host is different the device will send a NoACK.
R/W bit
bit 0
1 (R)
0 (W)
I²C Protocol:
(A) Write data procedure with designated address. (See Table 15)
1. Host transfers the start condition
2. Host transfers the device slave address with the write mode R/W bit (0).
3. Device sends ACK
4. Host transfers the corresponding memory address to the device
5. Device sends ACK
6. Host transfers the write data to the designated address
7. Device sends ACK
8. Routines (6) and (7) are repeated based on the transfer data, and the designated address is automatically incremented*
9. Host transfers the stop condition.
*Automatically incremented writes are not possible after a non−volatile write.
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