CAT5140 Datasheet, PDF (5/11 Pages) ON Semiconductor – Single Channel 256 Tap DPP with Integrated EEPROM and I2C Control

CAT5140
SCL
SDA
Start
Condition
Figure 2. Start and STOP Timing
Stop
Condition
t_F
SCL
t_SU:STA
SDA IN
SDA OUT
t_LOW
t_HIGH
t_HD:STA
t_HD:DAT
t_AA
t_R
t_SU:DAT
t_DH
Figure 3. Bus Timing
SCL from
Master
Bus Release Delay (Transmitter)
1
8
9
t_SU:STO
t_BUF
Bus Release
Delay (Receiver)
Data Output
from Transmitter
Data Output
from Receiver
Start
ACK Delay (≤ t_AA)
Figure 4. Acknowledge Timing
ACK Setup (≥ t_SU:DAT)
SCL
SDA IN
WP
Start
CLK1
t_SU:WP
Figure 5. WP Timing
Stop
t_HD:STO, t_HD:STO:NV
t_HD:WP
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