CAT34TS00 Datasheet, PDF (8/14 Pages) ON Semiconductor – Digital Temperature Sensor

CAT34TS00
Manufacturer ID Register (Read Only)
The manufacturer ID assigned by the PCI−SIG trade
organization to the CAT34TS00 device is fixed at 0x1B09.
Table 7. THE TEMPERATURE SENSOR REGISTERS
Register Address
Register Name
0x00
Capability Register
0x01
0x02
0x03
Configuration Register
High Limit Register
Low Limit Register
0x04
0x05
Critical Limit Register
Temperature Data Register
0x06
0x07
Manufacturer ID Register
Device ID/Revision Register
Device ID and Revision Register (Read Only)
This register contains specific device ID and device
revision information.
Power−On Default
0x0077
0x0000
0x0000
0x0000
0x0000
Undefined
0x1B09
0x2201
Read/Write
Read
Read/Write
Read/Write
Read/Write
Read/Write
Read
Read
Read
Table 8. CAPABILITY REGISTER
B15
B14
B13
RFU
(Note 9)
RFU
RFU
B7
B6
B5
EVSD
TMOUT
X
9. RFU stands for Reserved for Future Use
B12
RFU
B11
RFU
B4
B3
TRES [1:0]
B10
RFU
B2
RANGE
B9
RFU
B1
ACC
B8
RFU
B0
EVENT
Bit
Description
B15:B8
Reserved for future use; can not be written; should be ignored; will read as 0
B7 (Note 10)
0: Configuration Register bit 4 is frozen upon Configuration Register bit 8 being set
(i.e. a TS shut−down freezes the EVENT output)
1: Configuration Register bit 4 is cleared upon Configuration Register bit 8 being set
(i.e. a TS shut−down de−asserts the EVENT output)
B6
0: Not used
1: The TS implements SMBus time−out within the range 25 to 35 ms
B5
X: May be 0 or 1 (Default = 1)
B4:B3
00: LSB = 0.50°C (9 bit resolution)
01: LSB = 0.25°C (10 bit)
10: LSB = 0.125°C (11 bit)
11: LSB = 0.0625°C (12 bit)
B2
0: Not used
1: The temperature monitor can read temperatures below 0°C and sets the sign bit appropriately
B1
0: Not used
1: The temperature monitor has ±1°C accuracy over the active range (75°C to 95°C) and ±2°C
accuracy over the monitoring range (40°C to 125°C)
B0
0: Not used
1: The device supports interrupt capabilities
10. Configuration Register bit 4 can be cleared (but not set) after Configuration Register bit 8 is set, by writing a “1” to Configuration Register
bit 5 (EVENT output can be de−asserted during TS shut−down periods)
http://onsemi.com
8