CAT34C02VP2IGT4A Datasheet, PDF (8/14 Pages) ON Semiconductor – 2 kb I2C EEPROM for DDR2 DIMM Serial Presence Detect

CAT34C02
Software Write Protection
The lower half of memory (first 128 bytes) can be
protected against Write requests by setting one of two
Software Write Protection (SWP) flags.
The Permanent Software Write Protection (PSWP) flag
can be set or read while all address pins are at regular CMOS
levels (GND or V_CC), whereas the very high voltage V_HV
must be present on address pin A₀ to set, clear or read the
Reversible Software Write Protection (RSWP) flag. The
D.C. OPERATING CONDITIONS for RSWP operations
are shown in Table 8.
The SWP commands are listed in Table 9. All commands
are preceded by a START and terminated with a STOP,
following the ACK or NoACK from the CAT34C02. All
SWP related Slave addresses use the pre−amble: 0110 (6h),
instead of the regular 1010 (Ah) used for memory access.
For PSWP commands, the three address pins can be at any
logic level, whereas for RSWP commands the address pins
must be at pre−assigned logic levels. V_HV is interpreted as
logic ‘1’. The V_HV condition must be established on pin A₀
before the START and maintained just beyond the STOP.
Otherwise an RSWP request could be interpreted by the
CAT34C02 as a PSWP request.
The SWP Slave addresses follow the standard I²C
convention, i.e. to read the state of the SWP flag, the LSB of
the Slave address must be ‘1’, and to set or clear a flag, it
must be ‘0’. For Write commands a dummy byte address and
dummy data byte must be provided (Figure 14). In contrast
to a regular memory Read, a SWP Read does not return Data.
Instead the CAT34C02 will respond with NoACK if the flag
is set and with ACK if the flag is not set. Therefore, the
Master can immediately follow up with a STOP, as there is
no meaningful data following the ACK interval (Figure 15).
Hardware Write Protection
With the WP pin held HIGH, the entire memory, as well
as the SWP flags are protected against Write operations, see
Memory Protection Map below. If the WP pin is left floating
or is grounded, it has no impact on the operation of the
CAT34C02.
The state of the WP pin is strobed on the last falling edge
of SCL immediately preceding the first data byte (Figure 9).
If the WP pin is HIGH during the strobe interval, the
CAT34C02 will not acknowledge the data byte and the Write
request will be rejected.
FFH
Hardware Write Protectable
(by connecting WP pin to
V_CC)
7FH
Software Write Protectable
(by setting the write
protect flags)
00H
Figure 13. Memory Protection Map
Table 8. RSWP D.C. OPERATING CONDITIONS (Note 11)
Symbol
Parameter
Test Conditions
Min
Max
Units
DV_HV
A₀ Overdrive (V_HV − V_CC)
1.7 V < V_CC < 3.6 V
4.8
V
I_HVD
A₀ High Voltage Detector Current
0.1
mA
V_HV
A₀ Very High Voltage
7
10
V
I_HV
A₀ Input Current @ V_HV
1
mA
11. To prevent damaging the CAT34C02 while applying V_HV, it is strongly recommended to limit the power delivered to pin A₀, by inserting a series
resistor (> 1.5 kW) between the supply and the input pin. The resistance is only limited by the combination of V_HV and maximum I_HVD. While
the resistor can be omitted if V_HV is clamped well below 10 V, it nevertheless provides simple protection against EOS events.
As an example: V_CC = 1.7 V, V_HV = 8 V, 1.5 kW < R_S < 15 kW.
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