CAT34C02VP2IGT4A Datasheet, PDF (2/14 Pages) ON Semiconductor – 2 kb I2C EEPROM for DDR2 DIMM Serial Presence Detect

CAT34C02
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Unit
Operating Temperature
−45 to +130
°C
Storage Temperature
−65 to +150
°C
Voltage on Any Pin with Respect to Ground (Note 1)
−0.5 to +6.5
V
Voltage on Pin A₀ with Respect to Ground
−0.5 to +10.5
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V_CC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than V_CC + 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
Parameter
Min
Units
N_END (Note 3) Endurance
1,000,000
Program/ Erase Cycles
T_DR
Data Retention
100
Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, V_CC = 5 V, 25°C
Table 3. D.C. OPERATING CHARACTERISTICS (V_CC = 1.7 V to 5.5 V, T_A = −40°C to +85°C, unless otherwise specified.)
Symbol
Parameter
Test Conditions
Min
Max
Units
I_CC
Supply Current
I_SB
Standby Current
V_CC < 3.6 V, f_SCL = 100 kHz
V_CC > 3.6 V, f_SCL = 400 kHz
All I/O Pins at GND or V_CC
T_A = −40°C to +85°C
V_CC ≤ 3.3 V
1
mA
2
1
mA
T_A = −40°C to +85°C
3
V_CC > 3.3 V
I_L
I/O Pin Leakage
V_IL
Input Low Voltage
Pin at GND or V_CC
−0.5
2
mA
0.3 x V_CC
V
V_IH
Input High Voltage
V_OL
Output Low Voltage
V_CC > 2.5 V, I_OL = 3 mA
V_CC < 2.5 V, I_OL = 1 mA
0.7 x V_CC
V_CC + 0.5
0.4
0.2
Table 4. PIN IMPEDANCE CHARACTERISTICS (V_CC = 1.7 V to 5.5 V, T_A = −40°C to +85°C, unless otherwise specified.)
Symbol
Parameter
Conditions
Max
Units
C_IN (Note 4)
SDA I/O Pin Capacitance
Other Input Pins
V_IN = 0 V, f = 1.0 MHz, V_CC = 5.0 V
8
pF
6
I_WP (Note 5) WP Input Current
V_IN < V_IH, V_CC = 5.5 V
V_IN < V_IH, V_CC = 3.6 V
V_IN < V_IH, V_CC = 1.7 V
130
mA
120
80
V_IN > V_IH
2
I_A (Note 5)
Address Input Current
(A0, A1, A2)
Product Rev H
V_IN < V_IH, V_CC = 5.5 V
V_IN < V_IH, V_CC = 3.6 V
50
mA
35
V_IN < V_IH, V_CC = 1.7 V
25
V_IN > V_IH
2
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull-down is
relatively strong; therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To
conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V_CC), the strong pull-down reverts to a weak current
source.
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