PACVGA200_11 Datasheet, PDF (7/8 Pages) ON Semiconductor – VGA Port Companion Circuit

PACVGA200
APPLICATION INFORMATION
DDC_V_CC
VIDEO_DAC V_CC
0.2 mF 0.2 mF
5V
0.2 mF
R1 R2
0.2 mF
12
2
GNDD
14 13
DDC_Data
DDC_Clk
H−Sync
V−Sync
Red
Green
Blue
GNDD
16
17
19
21
8
9
ÎÎÎÎÎÎÎÎÎÎÎÎ ¹⁰
V_CC2 V_CC1
DDC_IN1
DDC_IN2
SYNC_IN1
SYNC_IN2
TERM_1
TERM_2
TERM_3
V_CC3 V_BIAS
1
V_CC4
11
PWR_UP
DDC_OUT1 ¹⁵
DDC_OUT2 ¹⁸
20
SYNC_OUT1
22
SYNC_OUT2
PACVGA200
3
VIDEO_1
4
VIDEO_2
5
VIDEO_3
23
SD1 ₂₄
SD2
ÎÎÎÎÎÎÎÎÎ
GNDA
7
GNDD
6
DDC_Data
DDC_Clk
H−Sync
V−Sync
R
G
B
VF** − VIDEO EMI Filter
SF** − SYNC EMI Filter
Figure 3. Typical Connection Diagram
A resistor may be necessary between the V_CC3 pin and ground if protection against a stream of ESD pulses is required while
the PACVGA200 is in the power−down state. The value of this resistor should be chosen such that the extra charge deposited
into the V_CC3 bypass capacitor by each ESD pulse will be discharged before the next ESD pulse occurs. The maximum ESD
repetition rate specified by the IEC−61000−4−2 standard is one pulse per second. When the PACVGA200 is in the power−up
state, an internal discharge resistor is connected to ground via an FET switch for this purpose.
For the same reason, V_CC1 and V_CC4 may also require bypass capacitor discharging resistors to ground if there are no other
components in the system to provide a discharge path to ground.
GNDA, the reference voltage for the 75 W resistors is not connected internally to GNDD and should ideally be connected
to the ground of the video DAC IC.
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