PACVGA200_11 Datasheet, PDF (5/8 Pages) ON Semiconductor – VGA Port Companion Circuit

PACVGA200
Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note 1)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
I_OFF Off−State Leakage Current,
Level−Shifting NFET
(V_CC2 − V_{DDC_IN})  0.4 V,
V_{DDC_OUT} = V_CC2
(V_CC2 − V_{DDC_OUT})  0.4 V,
V_{DDC_IN} = V_CC2
10
mA
10
V_ON Voltage Drop Across Level
V_CC2 = 2.5 V, V_S = GND, I_DS = 3 mA
Shifting NFET when Turned ON
0.15
V
C_IN
Input Capacitance
VIDEO_1,VIDEO_2 & VIDEO_3 V_CC1 = 5.0 V, V_IN = 2.5 V,
Inputs
Measured at 1 MHz
V_CC1 = 2.5 V, V_IN = 1.25 V,
Measured at 1 MHz
pF
3.0
4.0
5.0
3.0
4.5
5.6
t_PLH
SYNC Drivers L  H Propagation C_L = 50 pF, V_CC = 5.0 V,
Delay
Input t_R and t_F  5 ns
t_PHL
SYNC Drivers H  L Propagation C_L = 50 pF, V_CC = 5.0 V,
Delay
Input t_R and t_F  5 ns
8.0
12.0
ns
8.0
12.0
ns
t_R, t_F
SYNC Drivers Output Rise & Fall
Times
C_L = 50 pF, V_CC = 5.0 V,
Input t_R and t_F  5 ns
(Measured 10% − 90%)
5.0
7.0
10.0
ns
V_ESD ESD Withstand Voltage
V_CC1 = V_CC3 = V_CC4 = 5 V (Note 3)
8
kV
1. All parameters specified over standard operating conditions unless otherwise noted.
2. This parameter applies only to the HSYNC and VSYNC channels. HSYNC and VSYNC have 8 mA drivers with R_S added in series to
terminate transmission line.
3. Per the IEC−61000−4−2 International ESD Standard, Level 4 contact discharge method. V_CC1, V_CC3 and V_CC4 must be bypassed to GND
via a low impedance ground plane with a 0.2 mF, low inductance, chip ceramic capacitor at each supply pin. ESD pulse is applied between
the applicable pins and GND. ESD pulse can be positive or negative with respect to GND. Applicable pins are: VIDEO_1, VIDEO_2,
VIDEO_3, SYNC_OUT1, SD1, SYNC_OUT2, SD2, DDC_OUT1 and DDC_OUT2. All other pins are ESD protected to the industry standard
2 kV per the Human Body Model (MIL−STD−883, Method 3015).
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