PACVGA200_11 Datasheet, PDF (1/8 Pages) ON Semiconductor – VGA Port Companion Circuit

PACVGA200
VGA Port Companion Circuit
Product Description
The PACVGA200 incorporates seven channels of ESD protection
for all signal lines commonly found in a VGA port. ESD protection is
implemented with current steering diodes designed to safely handle
the high surge currents encountered with IEC−61000−4−2 Level−4
ESD Protection (8 kV contact discharge). When a channel is
subjected to an electrostatic discharge, the ESD current pulse is
diverted via the protection diodes into either the positive supply rail or
ground where it may be safely dissipated. Separate positive supply
rails are provided for the VIDEO, DDC and SYNC channels to
facilitate interfacing with low voltage Video Controller ICs and
provide design flexibility in multi−supply−voltage environments.
Two non−inverting drivers provide buffering for the HSYNC and
VSYNC signals from the Video Controller IC (SYNC_IN1,
SYNC_IN2). These buffers accept TTL input levels and convert them
to CMOS output levels that swing between Ground and V_CC4.
These drivers have nominal 60 W output impedance (R_S) to match
the characteristic impedance of the HSYNC & VSYNC lines of the
video cables typically used in PC applications. Two N−channel FETs
provide the level shifting function required when the DDC controller
is operated at a lower supply voltage than the monitor. Three 75 W
termination resistors suitable for terminating the video signals from
the video DAC are also provided. These resistors have separate input
pins to allow insertion of additional EMI filtering, if required, between
the termination point and the ESD protection diodes. These resistors
are matched to better than 2% for excellent signal level matching for
the R/G/B signals.
When the PWR_UP input is driven LOW, the SYNC inputs can be
floated without causing the SYNC buffers to draw any current from
the V_CC4 supply. When the PWR_UP input is LOW, the SYNC
outputs are driven LOW.
An internal diode (D1 in schematic on previous page) is also
provided so that V_CC3 can be derived from V_CC4, if desired, by
connecting V_CC3 to V_BIAS. In applications where V_CC4 may be
powered down, diode D1 blocks any DC current paths from the
DDC_OUT pins back to the powered down V_CC4 rail via the top ESD
protection diodes.
http://onsemi.com
QSOP24
QR SUFFIX
CASE 492B
MARKING DIAGRAM
PACVGA200QR
AWLYWW
PACVGA200QR = Specific Device Code
A
= Assembly Location
WL
= Wafer Lot
Y
= Year
WW
= Work Week
ORDERING INFORMATION
Device
Package
Shipping^†
PACVGA200QR QSOP24 2500/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Features
 Single Chip Solution for the VGA Port Interface
 Includes ESD Protection, Level Shifting, and RGB
Termination
 Seven Channels of ESD Protection for All VGA Port
Connector Pins Meeting IEC−61000−4−2 Level−4 ESD
Requirements (8 kV Contact Discharge)
 Very Low Loading Capacitance from ESD Protection
Diodes on VIDEO Lines, 4 pF Typical
 75 W Termination Resistors for VIDEO Lines
(Matched to 1% Typ.)
 TTL to CMOS Level−Translating Buffers with Power
Down Mode for HSYNC and VSYNC Lines
 Bi−Directional Level Shifting N−Channel FETs
Provided for DDC_CLK & DDC_DATA Channels
 Compact 24−Pin QSOP Package
 These Devices are Pb−Free and are RoHS Compliant
Applications
 Notebook Computers with VGA Port
 Desktop PCs with VGA Port
 Semiconductor Components Industries, LLC, 2011
1
October, 2011 − Rev. 3
Publication Order Number:
PACVGA200/D