MC74HC4046A_14 Datasheet, PDF (7/15 Pages) ON Semiconductor – Phase-Locked Loop

MC74HC4046A
The output of the VCO is a standard high speed CMOS
output with an equivalent LS−TTL fan out of 10. The VCO
output is approximately a square wave. This output can
either directly feed the COMP_IN of the phase comparators or
feed external prescalers (counters) to enable frequency
synthesis.
Phase Comparators
All three phase comparators have two inputs, SIG_IN and
COMP_IN. The SIG_IN and COMP_IN have a special DC bias
V_CC
SIG_IN
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network that enables AC coupling of input signals. If the
signals are not AC coupled, standard 74HC input levels are
required. Both input structures are shown in Figure 6. The
outputs of these comparators are essentially standard 74HC
outputs (comparator 2 is TRI−STATEABLE). In normal
operation V_CC and ground voltage levels are fed to the loop
filter. This differs from some phase detectors which supply
a current to the loop filter and should be considered in the
design. (The MC14046 also provides a voltage).
V_CC
PC2_OUT
13
V_CC
COMP_IN
3
PCP_OUT
1
PC3_OUT
15
PC1_OUT
2
Figure 6. Logic Diagram for Phase Comparators
Phase Comparator 1
This comparator is a simple XOR gate similar to the
74HC86. Its operation is similar to an overdriven balanced
modulator. To maximize lock range the input frequencies
must have a 50% duty cycle. Typical input and output
waveforms are shown in Figure 7. The output of the phase
detector feeds the loop filter which averages the output
voltage. The frequency range upon which the PLL will lock
onto if initially out of lock is defined as the capture range.
The capture range for phase detector 1 is dependent on the
loop filter design. The capture range can be as large as the
lock range, which is equal to the VCO frequency range.
To see how the detector operates, refer to Figure 7. When
two square wave signals are applied to this comparator, an
output waveform (whose duty cycle is dependent on the
phase difference between the two signals) results. As the
phase difference increases, the output duty cycle increases
and the voltage after the loop filter increases. In order to
achieve lock when the PLL input frequency increases, the
VCO input voltage must increase and the phase difference
between COMP_IN and SIG_IN will increase. At an input
frequency equal to f_min, the VCO input is at 0 V. This
requires the phase detector output to be grounded; hence, the
two input signals must be in phase. When the input
frequency is f_max, the VCO input must be V_CC and the phase
detector inputs must be 180 degrees out of phase.
SIG_IN
COMP_IN
PC1_OUT
V_CC
VCO_IN
GND
Figure 7. Typical Waveforms for PLL Using
Phase Comparator 1
The XOR is more susceptible to locking onto harmonics
of the SIG_IN than the digital phase detector 2. For instance,
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