MC74HC4046A_14 Datasheet, PDF (1/15 Pages) ON Semiconductor – Phase-Locked Loop

MC74HC4046A
Phase-Locked Loop
High−Performance Silicon−Gate CMOS
The MC74HC4046A is similar in function to the MC14046 Metal
gate CMOS device. The device inputs are compatible with standard
CMOS outputs; with pullup resistors, they are compatible with
LSTTL outputs.
The HC4046A phase−locked loop contains three phase
comparators, a voltage−controlled oscillator (VCO) and unity gain
op−amp DEM_OUT. The comparators have two common signal inputs,
COMP_IN, and SIG_IN. Input SIG_IN and COMP_IN can be used directly
coupled to large voltage signals, or indirectly coupled (with a series
capacitor to small voltage signals). The self−bias circuit adjusts small
voltage signals in the linear region of the amplifier. Phase comparator
1 (an exclusive OR gate) provides a digital error signal PC1_OUT and
maintains 90 degrees phase shift at the center frequency between
SIG_IN and COMP_IN signals (both at 50% duty cycle). Phase
comparator 2 (with leading−edge sensing logic) provides digital error
signals PC2_OUT and PCP_OUT and maintains a 0 degree phase shift
between SIG_IN and COMP_IN signals (duty cycle is immaterial). The
linear VCO produces an output signal VCO_OUT whose frequency is
determined by the voltage of input VCO_IN signal and the capacitor
and resistors connected to pins C1A, C1B, R1 and R2. The unity gain
op−amp output DEM_OUT with an external resistor is used where the
VCO_IN signal is needed but no loading can be tolerated. The inhibit
input, when high, disables the VCO and all op−amps to minimize
standby power consumption.
Applications include FM and FSK modulation and demodulation,
frequency synthesis and multiplication, frequency discrimination,
tone decoding, data synchronization and conditioning,
voltage−to−frequency conversion and motor speed control.
Features
• Output Drive Capability: 10 LSTTL Loads
• Low Power Consumption Characteristic of CMOS Devices
• Operating Speeds Similar to LSTTL
• Wide Operating Voltage Range: 3.0 to 6.0 V
• Low Input Current: 1.0 mA Maximum (except SIG_IN and COMP_IN)
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7 A
• Low Quiescent Current: 80 mA Maximum (VCO disabled)
• High Noise Immunity Characteristic of CMOS Devices
• Diode Protection on all Inputs
• Chip Complexity: 279 FETs or 70 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free and are RoHS Compliant
http://onsemi.com
SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
PIN ASSIGNMENT
PCP_out 1
PC1_out 2
COMP_in 3
VCO_out 4
INH 5
C1A 6
C1B 7
GND 8
16 V_CC
15 PC3_out
14 SIG_in
13 PC2_out
12 R2
11 R1
10 DEM_out
9 VCO_in
MARKING DIAGRAMS
16
HC4046AG
AWLYWW
1
SOIC−16
16
HC40
46A
ALYWG
G
1
TSSOP−16
A
L, WL
Y, YY
W, WW
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
August, 2014 − Rev. 11
Publication Order Number:
MC74HC4046A/D