MC74HC4046A_14 Datasheet, PDF (3/15 Pages) ON Semiconductor – Phase-Locked Loop

MC74HC4046A
[Phase Comparator Section]
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol
V_IH
V_IL
V_OH
Parameter
Minimum High−Level Input
Voltage DC Coupled
SIG_IN, COMP_IN
Maximum Low−Level Input
Voltage DC Coupled
SIG_IN, COMP_IN
Minimum High−Level
Output Voltage
PCP_OUT, PCn_OUT
Test Conditions
V_out = 0.1 V or V_CC − 0.1 V
|I_out| ≤ 20 mA
V_out = 0.1 V or V_CC − 0.1 V
|I_out| ≤ 20 mA
V_in = V_IH or V_IL
|I_out| ≤ 20 mA
V_in = V_IH or V_IL
|I_out| ≤ 4.0 mA
|I_out| ≤ 5.2 mA
V_CC
Guaranteed Limit
V –55 to 25_C ≤ 85°C ≤ 125°C Unit
2.0
1.5
4.5
3.15
6.0
4.2
1.5
1.5
V
3.15
3.15
4.2
4.2
2.0
0.5
4.5
1.35
6.0
1.8
0.5
0.5
V
1.35
1.35
1.8
1.8
2.0
1.9
4.5
4.4
6.0
5.9
1.9
1.9
V
4.4
4.4
5.9
5.9
4.5
3.98
6.0
5.48
3.84
3.7
5.34
5.2
V_OL
Maximum Low−Level
Output Voltage Qa−Qh
PCP_OUT, PCn_OUT
V_out = 0.1 V or V_CC − 0.1 V
2.0
0.1
|I_out| ≤ 20 mA
4.5
0.1
6.0
0.1
V_in = V_IH or V_IL
|I_out| ≤ 4.0 mA
|I_out| ≤ 5.2 mA
4.5
0.26
6.0
0.26
0.1
0.1
V
0.1
0.1
0.1
0.1
0.33
0.4
0.33
0.4
I_in
Maximum Input Leakage Current
V_in = V_CC or GND
2.0
SIG_IN, COMP_IN
3.0
4.5
6.0
I_OZ
Maximum Three−State
Leakage Current
PC2_OUT
Output in High−Impedance State 6.0
V_in = V_IH or V_IL
V_out = V_CC or GND
I_CC
Maximum Quiescent Supply Current V_in = V_CC or GND
6.0
(per Package) (VCO disabled)
|I_out| = 0 mA
Pins 3, 5 and 14 at V_CC
Pin 9 at GND; Input Leakage at
Pins 3 and 14 to be excluded
±3.0
±7.0
±18.0
±30.0
±0.5
4.0
±4.0
±5.0
mA
±9.0
±11.0
±23.0
±27.0
±38.0
±45.0
±5.0
±10
mA
40
160
mA
[Phase Comparator Section]
AC ELECTRICAL CHARACTERISTICS (C_L = 50 pF, Input t_r = t_f = 6.0 ns)
Symbol
t_PLH,
t_PHL
Parameter
Maximum Propagation Delay, SIG_IN/COMP_IN to PC1_OUT
(Figure 1)
t_PLH,
t_PHL
Maximum Propagation Delay, SIG_IN/COMP_IN to PCP_OUT
(Figure 1)
t_PLH,
t_PHL
Maximum Propagation Delay, SIG_IN/COMP_IN to PC3_OUT
(Figure 1)
t_PLZ,
t_PHZ
Maximum Propagation Delay, SIG_IN/COMP_IN Output
Disable Time to PC2_OUT (Figures 2 and 3)
t_PZH,
t_PZL
Maximum Propagation Delay, SIG_IN/COMP_IN Output
Enable Time to PC2_OUT (Figures 2 and 3)
t_TLH,
t_THL
Maximum Output Transition Time
(Figure 1)
V_CC
Guaranteed Limit
V –55 to 25_C ≤ 85°C ≤ 125°C Unit
2.0
175
4.5
35
6.0
30
220
265
ns
44
53
37
45
2.0
340
4.5
68
6.0
58
425
510
ns
85
102
72
87
2.0
270
4.5
54
6.0
46
340
405
ns
68
81
58
69
2.0
200
4.5
40
6.0
34
250
300
ns
50
60
43
51
2.0
230
4.5
46
6.0
39
290
345
ns
58
69
49
59
2.0
75
4.5
15
6.0
13
95
110
ns
19
22
16
19
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