CM1293 Datasheet, PDF (7/10 Pages) California Micro Devices Corp – 2, 4, and 8-Channel Low Capacitance ESD Protection Arrays

CM1293
Application Information
Design Considerations
In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to
minimize parasitic series inductances on the Supply/Ground rails as well as the signal trace segment between
the signal input (typically a connector) and the ESD protection device. Refer to Application of Positive ESD
Pulse between Input Channel and Ground, which illustrates an example of a positive ESD pulse striking an
input channel. The parasitic series inductance back to the power supply is represented by L₁ and L₂. The
voltage V_CL on the line being protected is:
V_CL = Fwd voltage drop of D₁ + V_SUPPLY + L₁ x d(I_ESD) / dt+ L₂ x d(I_ESD) / dt
where I_ESD is the ESD current pulse, and V_SUPPLY is the positive supply voltage.
An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact
discharge per the IEC61000-4-2 standard results in a current pulse that rises from zero to 30 Amps in 1ns.
Here d(I_ESD)/dt can be approximated by ΔI_ESD/Δt, or 30/(1x10^-9). So just 10nH of series inductance (L₁ and L₂
combined) will lead to a 300V increment in V_CL!
Similarly for negative ESD pulses, parasitic series inductance from the V_N pin to the ground rail will lead to
drastically increased negative voltage on the line being protected.
The CM1293 has an integrated Zener diode between V_P and V_N. This greatly reduces the effect of supply rail
inductance L₂ on V_CL by clamping V_P at the breakdown voltage of the Zener diode. However, for the lowest
possible V_CL, especially when V_P is biased at a voltage significantly below the Zener breakdown voltage, it is
recommended that a 0.22μF ceramic chip capacitor be connected between V_P and the ground plane.
As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of
expected electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to
the V_P pin of the Protection Array as possible, with minimum PCB trace lengths to the power supply, ground
planes and between the signal input and the ESD device to minimize stray series inductance.
Figure 3. Application of Positive ESD Pulse between Input Channel and Ground
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