CAT34C02 Datasheet, PDF (7/15 Pages) Catalyst Semiconductor – 2-Kb I2C EEPROM for DDR2 DIMM Serial Presence Detect

CAT34C02
Read Operations
Immediate Address Read
In standby mode, the CAT34C02 internal address counter
points to the data byte immediately following the last byte
accessed by a previous operation. If that ‘previous’ byte was
the last byte in memory, then the address counter will point
to the 1^st memory byte, etc.
When, following a START, the CAT34C02 is presented
with a Slave address containing a ‘1’ in the R/W bit position
(Figure 10), it will acknowledge (ACK) in the 9^th clock cycle,
and will then transmit data being pointed at by the internal
address counter. The Master can stop further transmission by
issuing a NoACK, followed by a STOP condition.
Selective Read
The Read operation can also be started at an address
different from the one stored in the internal address counter.
The address counter can be initialized by performing a
‘dummy’ Write operation (Figure 11). Here the START is
followed by the Slave address (with the R/W bit set to ‘0’)
and the desired byte address. Instead of following up with
data, the Master then issues a 2^nd START, followed by the
‘Immediate Address Read’ sequence, as described earlier.
Sequential Read
If the Master acknowledges the 1^st data byte transmitted
by the CAT34C02, then the device will continue
transmitting as long as each data byte is acknowledged by
the Master (Figure 12). If the end of memory is reached
during sequential Read, then the address counter will
‘wrap−around’ to the beginning of memory, etc. Sequential
Read works with either ‘Immediate Address Read’ or
‘Selective Read’, the only difference being the starting byte
address.
S
T
S
BUS ACTIVITY: ^A
SLAVE
T
MASTER ^R ADDRESS
O
T
P
SDA LINE S
P
A
N
C
DATA
O
K
A
C
K
SCL
8
9
SDA
8th Bit
DATA OUT
NO ACK
Figure 10. Immediate Address Read Timing
STOP
S
S
T
T
S
BUS ACTIVITY: ^A
SLAVE
BYTE
A
SLAVE
T
MASTER ^R ADDRESS
ADDRESS (n) ^R ADDRESS
O
T
T
P
SDA LINE S
S
P
A
A
C
C
K
K
Figure 11. Selective Read Timing
A
N
C ^{DATA n}
O
K
A
C
K
BUS ACTIVITY: SLAVE
MASTER ADDRESS
SDA LINE
A
C
K
DATA n
DATA n+1
DATA n+2
A
A
A
C
C
C
K
K
K
Figure 12. Sequential Read Timing
S
T
DATA n+x
O
P
P
N
O
A
C
K
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