CAT34C02 Datasheet, PDF (5/15 Pages) Catalyst Semiconductor – 2-Kb I2C EEPROM for DDR2 DIMM Serial Presence Detect

CAT34C02
1
0
1
0 A₂ A₁ A₀ R/W
DEVICE ADDRESS
Figure 3. Slave Address Bits
SCL FROM
MASTER
BUS RELEASE DELAY (TRANSMITTER)
1
8
BUS RELEASE DELAY
(RECEIVER)
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACK DELAY (≤ t_AA)
Figure 4. Acknowledge Timing
ACK SETUP (≥ t_SU:DAT)
t_F
t_HIGH
t_R
t_LOW
t_LOW
SCL
t_SU:STA
SDA IN
t_HD:STA
t_HD:DAT
t_SU:DAT
SDA OUT
t_AA
t_DH
t_SU:STO
t_BUF
Figure 5. Bus Timing
Write Operations
Byte Write
In Byte Write mode the Master sends a START, followed
by Slave address, byte address and data to be written
(Figure 6). The Slave acknowledges all 3 bytes, and the
Master then follows up with a STOP, which in turn starts the
internal Write operation (Figure 7). During internal Write,
the Slave will not acknowledge any Read or Write request
from the Master.
Page Write
The CAT34C02 contains 256 bytes of data, arranged in 16
pages of 16 bytes each. A page is selected by the 4 most
significant bits of the address byte following the Slave
address, while the 4 least significant bits point to the byte
within the page. Up to 16 bytes can be written in one Write
cycle (Figure 8).
The internal byte address counter is automatically
incremented after each data byte is loaded. If the Master
transmits more than 16 data bytes, then earlier bytes will be
overwritten by later bytes in a ‘wrap−around’ fashion
(within the selected page). The internal Write cycle starts
immediately following the STOP.
Acknowledge Polling
Acknowledge polling can be used to determine if the
CAT34C02 is busy writing or is ready to accept commands.
Polling is implemented by interrogating the device with a
‘Selective Read’ command (see READ OPERATIONS).
The CAT34C02 will not acknowledge the Slave address,
as long as internal Write is in progress.
Delivery State
The CAT34C02 is shipped ‘unprotected’, i.e. neither SWP
flag is set. The entire 2 kb memory is erased, i.e. all bytes are
FFh.
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