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NSS40200L_16 Datasheet, PDF (6/6 Pages) ON Semiconductor – PNP Transistor | |||
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NSS40200L, NSV40200L
PACKAGE DIMENSIONS
SOTâ23 (TOâ236)
CASE 318â08
ISSUE AR
E
A
A1
D
3
1
2
e
TOP VIEW
SIDE VIEW
HE
3X b
0.25
T
L
L1
VIEW C
SEE VIEW C
c
END VIEW
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH.
MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF
THE BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
MILLIMETERS
DIM MIN NOM MAX
A 0.89
1.00
1.11
A1 0.01
0.06
0.10
b
0.37
0.44
0.50
c
0.08
0.14
0.20
D 2.80
2.90
3.04
E 1.20
1.30
1.40
e
1.78
1.90
2.04
L 0.30
0.43
0.55
L1 0.35
0.54
0.69
H E 2.10
T
0°
2.40
âââ
2.64
10°
MIN
0.035
0.000
0.015
0.003
0.110
0.047
0.070
0.012
0.014
0.083
0°
INCHES
NOM
0.039
0.002
0.017
0.006
0.114
0.051
0.075
0.017
0.021
0.094
âââ
MAX
0.044
0.004
0.020
0.008
0.120
0.055
0.080
0.022
0.027
0.104
10°
STYLE 6:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
RECOMMENDED
SOLDERING FOOTPRINT*
2.90
3X
0.90
3X 0.80
0.95
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our PbâFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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NSS40200L/D
6
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