MC74VHCT259A Datasheet, PDF (6/9 Pages) ON Semiconductor – 8−Bit Addressable Latch/1−of−8 Decoder CMOS Logic Level Shifter with LSTTL−Compatible Inputs

MC74VHCT259A
TIMING REQUIREMENTS (Input t_r = t_f = 3.0ns)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Symbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^tw
Parameter
Minimum Pulse Width, Reset or Enable
(Figure 10)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{tsu Minimum Setup Time, Address or Data to Enable}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{(Figure 10)}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _th
Minimum Hold Time, Enable to Address or Data
(Figure 8 or 9)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^tr, ^tf ^{Maximum Input, Rise and Fall Times}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{(Figure 6)}
Test Conditions
V_CC = 3.3 ± 0.3V
V_CC = 5.0 ± 0.5V
V_CC = 3.3 ± 0.3V
V_CC = 5.0 ± 0.5V
V_CC = 3.3 ± 0.3V
V_CC = 5.0 ± 0.5V
V_CC = 3.3 ± 0.3V
V_CC = 5.0 ± 0.5V
T_A = 25°C
Min Typ Max
5.0
5.0
4.5
3.0
2.0
2.0
400
200
T_A = ≤ 85°C T_A = ≤ 125°C
Min Max Min Max Unit
5.5
5.5
ns
5.5
5.5
4.5
4.5
ns
3.0
3.0
2.0
2.0
ns
2.0
2.0
300
300 ns
100
100
t_r
DATA IN
50%
t_PLH
50%
OUTPUT Q
DATA IN
t_f
V_CC ADDRESS
SELECT
GND
t_PHL
OUTPUT Q
Figure 6. Switching Waveform
50%
50%
t_PHL
V_CC
GND
V_CC
GND
V_CC
GND
t_PHL
50%
Figure 7. Switching Waveform
V_CC
V_CC
DATA IN
GND
DATA IN
GND
t_w
t_w
ENABLE
V_CC
RESET
t_w
V_CC
50%
50%
50%
50%
GND
GND
t_PHL
t_PHL
t_PHL
OUTPUT Q
OUTPUT Q
50%
Figure 8. Switching Waveform
Figure 9. Switching Waveform
DATA IN
OR
50%
ADDRESS
SELECT
t_su
t_h(H)
t_su
ENABLE
50%
Figure 10. Switching Waveform
V_CC
GND
t_h(H)
V_CC
GND
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
C_L*
*Includes all probe and jig capacitance
Figure 11. Test Circuit
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