CAT64LC40 Datasheet, PDF (6/12 Pages) ON Semiconductor – 4 kb SPI Serial EEPROM

CAT64LC40
The CAT64LC40 requires an active LOW CS in order to
be selected. Each instruction must be preceded by a
HIGH−to−LOW transition of CS before the input of the
4−bit start sequence. Prior to the 4−bit start sequence (1010),
the device will ignore inputs of all other logical sequence.
Read
Upon receiving a READ command and address (clocked
into the DI pin), the DO pin will output data one t_PD after the
falling edge of the 16th clock (the last bit of the address
field). The READ operation is not affected by the RESET
input.
Write
After receiving a WRITE op code, address and data, the
device goes into the AUTO−Clear cycle and then the
WRITE cycle. The RDY/BSY pin will output the BUSY
status (LOW) one t_SV after the rising edge of the 32^nd clock
(the last data bit) and will stay LOW until the write cycle is
complete. Then it will output a logical “1” until the next
WRITE cycle. The RDY/BSY output is not affected by the
input of CS.
RESET
SK
CS
DI
1 01 00 1 00
ADDRESS*
D15
D0
DO
RDY/BUSY
Figure 5. Write Instruction Timing
*Please check instruction set table for address.
RESET
LOW
SK
CS
WRITE INSTRUCTION
DI
NEXT INSTRUCTION
DO
RDY/BUSY
HIGH
Figure 6. Ready/BUSY Status Instruction Timing
http://onsemi.com
6