2N5087_07 Datasheet, PDF (6/7 Pages) ON Semiconductor – Amplifier Transistor PNP Silicon

2N5087
1.0
0.7
0.5
D = 0.5
0.3
0.2
0.2
0.1
0.1
0.07
0.05
0.05
0.02
0.03
0.02
0.01
SINGLE PULSE
0.01
0.01 0.02 0.05 0.1 0.2 0.5 1.0 2.0
FIGURE 19
P_(pk)
t₁
t₂
DUTY CYCLE, D = t₁/t₂
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t₁ (SEE AN569)
Z_qJA(t) = r(t) w R_qJA
T_J(pk) − T_A = P_(pk) Z_qJA(t)
5.0 10 20 50 100 200
t, TIME (ms)
500 1.0 k 2.0 k 5.0 k 10 k 20 k 50 k 100 k
Figure 17. Thermal Response
400
1.0 ms
10 ms
200
100 ms
100
T_C = 25°C
1.0 s
60
dc
T_A = 25°C
40
dc
20
T_J = 150°C
10
CURRENT LIMIT
6.0
THERMAL LIMIT
SECOND BREAKDOWN LIMIT
4.0
2.0
4.0 6.0 8.0 10
20
40
V_CE, COLLECTOR−EMITTER VOLTAGE (VOLTS)
Figure 18. Active−Region Safe Operating Area
10⁴
V_CC = 30 V
10³
10²
10¹
10⁰
I_CEO
I_CBO
AND
I_CEX @ V_BE(off) = 3.0 V
The safe operating area curves indicate I_C−V_CE limits of
the transistor that must be observed for reliable operation.
Collector load lines for specific circuits must fall below the
limits indicated by the applicable curve.
The data of Figure 18 is based upon T_J(pk) = 150°C; T_C or
T_A is variable depending upon conditions. Pulse curves are
valid for duty cycles to 10% provided T_J(pk) ≤ 150°C. T_J(pk)
may be calculated from the data in Figure 17. At high case
or ambient temperatures, thermal limitations will reduce the
power than can be handled to values less than the limitations
imposed by second breakdown.
DESIGN NOTE: USE OF THERMAL RESPONSE DATA
A train of periodical power pulses can be represented by
the model as shown in Figure 19. Using the model and the
device thermal response the normalized effective transient
thermal resistance of Figure 17 was calculated for various
duty cycles.
To find Z_qJA(t), multiply the value obtained from Figure
17 by the steady state value R_qJA.
Example:
The 2N5087 is dissipating 2.0 watts peak under the follow-
ing conditions:
t₁ = 1.0 ms, t₂ = 5.0 ms (D = 0.2)
Using Figure 17 at a pulse width of 1.0 ms and D = 0.2, the
reading of r(t) is 0.22.
10^−1
10^−2
− 40 − 20
The peak rise in junction temperature is therefore
DT = r(t) x P_(pk) x R_qJA = 0.22 x 2.0 x 200 = 88°C.
For more information, see ON Semiconductor Application
0 + 20 + 40 + 60 + 80 + 100 + 120 + 140 + 160 Note AN569/D, available from the Literature Distribution
T_J, JUNCTION TEMPERATURE (°C)
Center or on our website at www.onsemi.com.
Figure 19. Typical Collector Leakage Current
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