NOIV1SE2000A-QDC Datasheet, PDF (52/77 Pages) ON Semiconductor – VITA 2000 2.3 Megapixel 92 FPS Global Shutter CMOS Image Sensor

NOIV1SN2000A, NOIV2SN2000A
Table 36. REGISTER MAP
Address
Offset
Address
Bit Field
[1]
Register Name
mux_pwd_n
[2]
colbias_enable
1
41
AFE [Block Offset:48]
0
48
[3:0]
[7:4]
[10:8]
[12:11]
[13]
[14]
[15]
image_core_config
dac_ds
dac_ts
reserved
reserved
reserved
reserved
reserved
power_down
[0]
pwd_n
Bias [Block Offset: 64]
0
64
power_down
[0]
pwd_n
1
65
configuration
[0]
extres
[3:1]
reserved
[7:4]
imc_colpc_ibias
[11:8]
imc_colbias_ibias
[15:12] cp_ibias
2
66
afe_bias
[3:0]
afe_ibias
[7:4]
afe_adc_iref
[14:8]
afe_pga_iref
3
67
mux_bias
[3:0]
mux_25u_stage1
[7:4]
mux_25u_stage2
[15:8]
reserved
4
68
lvds_bias
Default Default
(Hex) (Dec)
Description
0x0
0
Column multiplexer Power down
‘0’ = powered down,
‘1’ = powered up
0x0
0
Bias enable
‘0’ = disabled
‘1’ = enabled
0xB5A 2906
0xA
10 Double slope reset level
0x5
5
Triple slope reset level
0x3
3
Reserved
0x1
1
Reserved
0x0
0
Reserved
0x0
0
Reserved
0x0
0
Reserved
Type
RW
0x0000
0x0
0
RW
0
Power down for AFEs (8 columns)
‘0’ = powered down,
‘1’ = powered up
0x0000
0
RW
0x0
0
Power down bandgap
‘0’ = powered down,
‘1’ = powered up
0x888B 34955
RW
0x1
1
External resistor selection
‘0’ = internal resistor,
‘1’ = external resistor
0x5
5
Reserved
0x8
8
Column precharge ibias Configur-
ation
0x8
8
Column bias ibias configuration
0x8
8
Charge pump bias
0x53C8 21448
RW
0x8
8
AFE ibias configuration
0xC
12 ADC iref configuration
0x53
83 PGA iref configuration
0x8888 34952
RW
0x8
8
Column multiplexer stage 1 bias
configuration
0x8
8
Column multiplexer stage 2 bias
configuration
0x88
72 Reserved
0x0088 136
RW
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