NOIV1SE2000A-QDC Datasheet, PDF (17/77 Pages) ON Semiconductor – VITA 2000 2.3 Megapixel 92 FPS Global Shutter CMOS Image Sensor

NOIV1SN2000A, NOIV2SN2000A
User Actions: Power Up Functional Mode Sequences
Power Up Sequence
Figure 12 shows the power up sequence of the sensor. The
figure indicates that the first supply to ramp-up is the vdd_18
supply, followed by vdd_33 and vdd_pix respectively. It is
important to comply with the described sequence. Any other
supply ramping sequence may lead to high current peaks
and, as consequence, a failure of the sensor power up.
The clock input should start running when all supplies are
stabilized. When the clock frequency is stable, the reset_n
signal can be de-asserted. After a wait period of 10 ms, the
power up sequence is finished and the first SPI upload can
be initiated.
NOTE: The ‘clock input’ can be the CMOS PLL clock
input (clk_pll), or the LVDS clock input
(lvds_clock_inn/p) in case the PLL is bypassed.
clock input
reset_n
vdd_18
vdd_33
vdd_pix
SPI Upload
> 10us > 10us > 10us
> 10us
> 10us
Figure 12. Power Up Sequence
Enable Clock Management − Part 1
The ‘Enable Clock Management’ action configures the
clock management blocks and activates the clock generation
and distribution circuits in a pre-defined way. First, a set of
clock settings must be uploaded through the SPI register.
These settings are dependent on the desired operation mode
of the sensor.
Table 6 shows the SPI uploads to be executed to configure
the sensor for V1-SN/SE 8-bit serial, V1-SN/SE 10-bit
serial, or V2-SN/SE 10-bit parallel mode, with and without
the PLL.
In the serial modes, if the PLL is not used, the LVDS clock
input must be running.
In the V2-SN/SE10-bit parallel mode, the PLL is
bypassed. The clk_pll clock is used as sensor clock.
It is important to follow the upload sequence listed in
Table 6.
Use of Phase Locked Loop
If PLL is used, the PLL is started after the upload of the
SPI registers. The PLL requires (dependent on the settings)
some time to generate a stable output clock. A lock detect
circuit detects if the clock is stable. When complete, this is
flagged in a status register.
NOTE: The lock detect status must not be checked for
the V2-SN/SE sensor.
Check this flag by reading the SPI register. When the flag
is set, the ‘Enable Clock Management- Part 2’ action can be
continued. When PLL is not used, this step can be bypassed
as shown in Figure 11 on page 16.
Table 6. ENABLE CLOCK MANAGEMENT REGISTER UPLOAD − PART 1
Upload #
Address
Data
Description
V1-SN/SE 8-bit mode with PLL
1
2
0x0000
Monochrome sensor
0x0001
Color sensor
2
32
0x200C
Configure clock management
3
20
0x0000
Configure clock management
4
17
0X210F
Configure PLL
5
26
0x1180
Configure PLL lock detector
6
27
0xCCBC
Configure PLL lock detector
7
8
0x0000
Release PLL soft reset
8
16
0x0003
Enable PLL
V1-SN/SE 8-bit mode without PLL
1
2
0x0000
Monochrome sensor
0x0001
Color sensor
2
32
0x2008
Configure clock management
3
20
0x0001
Enable LVDS clock input
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