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| NOIH2SM1000A Datasheet, PDF (51/66 Pages) ON Semiconductor – HAS2 Image Sensor | |||
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NOIH2SM1000A
Sensor Programming
Parallel Sensor Programming Interface
The operational modes and start-of-window addresses of
the HAS are kept in seven on-chip registers. These internal
registers are programmable through a parallel interface
similar to the one on the STAR250.
This interface comprises of a 10-bit wide A bus, and 3 load
strobes: LD_X, LD_Y, and LD_REG.
With LD_Y or LD_X asserted (rising edge), the full 10
bits of A are loaded into respectively the line start address
(Y1) and the column start address (X1) (as similar to the
STAR250).
With a rising edge on LD_REG, the upper two bits of A
are decoded as an internal register address, and the 8 lower
bits of A are loaded into the corresponding register. These 4
registers are reset to their default values by asserting
RES_REGn.
Address Register Load Timing Diagram
t1
t4
A
X1/Y1
LâD_X/LD_Y
X1/Y1
XXX
t2
t3
X1/Y1
Figure 42. Line / Column Address Upload Timing Diagram
The YRD/YRST and XRD pointer start address registers
Y1 and X1 are latches that pass the input value when
LD_Y/LD_X is asserted, and freeze their output values
when LD_Y/LD_X is deasserted.
Description
t1
A setup
t2
LD_* width
t3
delay
t4
A hold
Min
Typ
Max
100 ns
100 ns
75 ns
100 ns
Remarks
t1
t4
A
value
t2
LDâ_RâEG
t3
regâiâsâteâr
XXX
value
Figure 43. Mode Registers Upload Timing Diagram
The mode setting registers are edge-triggered flip flops
that freeze their outputs at the rising edge of LD_REG.
Description
t1
A setup
t2
LD_REG width
t3
delay
t4
A hold
Min
Typ
Max
100 ns
100 ns
75 ns
100 ns
Remarks
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