AP0202AT Datasheet, PDF (50/54 Pages) ON Semiconductor – High-Dynamic Range Image Signal Processor

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AP0202AT: Image Signal Processor (ISP)
Two-Wire Serial Register Interface
Two-Wire Serial Register Interface
The electrical characteristics of the two-wire serial register interface (SCLK, SDATA) are
shown in Figure 30 and Table 34.
Figure 30: Slave Two Wire Serial Bus Timing Parameters (CCIS)
SDATA
tf
SCLK
S
tLOW
tr
tSU;DAT
tf
tHD;STA
tHD;DAT
tHIGH
tSU;STA
tHD;STA
Sr
tr
tBUF
tSU;STO
P
S
Table 34:
Slave Two-Wire Serial Bus Characteristics (CCIS)
Default Setup Conditions: fEXTCLK = 27 MHz; VDDIO_H = VDD_OTPM = 2.8V; VDD_REG = VDDIO_S = 1.8V; T_A = 25°C unless
otherwise stated
Standard-Mode
Fast-Mode
Parameter
SCLK Clock Frequency
Hold time (repeated) START condition.
After this period, the first clock pulse is generated
LOW period of the SCLK clock
HIGH period of the SCLK clock
Set-up time for a repeated START condition
Data hold time
Data set-up time
Rise time of both SDATA and SCLK signals (10-90%)
Fall time of both SDATA and SCLK signals (10-90%)
Set-up time for STOP condition
Bus free time between a STOP and START
condition
Capacitive load for each bus line
Serial interface input pin capacitance
SDATA max load capacitance
SDATA pull-up resistor
Symbol
f_SCL
t_HD;STA
t_LOW
t_HIGH
t_SU;STA
t_HD;DAT
t_SU;DAT
t_r
t_f
t_SU;STO
t_BUF
Cb
C_{IN_SI}
C_{LOAD_SD}
R_SD
Min
Max
Min
Max
Unit
0
100
0
400
KHz
4.0
-
0.6
-
s
4.7
-
1.3
-
s
4.0
-
0.6
-
s
4.7
-
0.6
-
s
0²
3.45³
0
0.9³
Ss
250
-
100
-
ns
-
1000 20 + 0.1Cb⁴ 300
ns
-
300
20 + 0.1Cb⁴ 300
ns
4.0
-
0.6
-
s
4.7
-
1.3
-
s
-
400
-
400
pF
-
3.3
-
3.3
pF
-
30
-
30
pF
1.5
4.7
1.5
4.7
K
Notes:
1. All values referred to VIHmin = 0.9 VDDIO_H and VILmax = 0.1 VDDIO_H levels. EXCLK = 27 MHz.
2. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the
undefined region of the falling edge of SCLK.
3. The maximum t_HD;DAT has only to be met if the device does not stretch the LOW period (t_LOW) of
the SCLK signal.
4. Cb = total capacitance of one bus line in pF.
AP0202AT/D Rev. 4, Pub. 9/15 EN
50
©Semiconductor Components Industries, LLC, 2015.