NSTB1005DXV5_04 Datasheet, PDF (5/6 Pages) ON Semiconductor – Dual Common Base-Collector Bias Resistor Transistors

NSTB1005DXV5T1, NSTB1005DXV5T5
PACKAGE DIMENSIONS
SOT−553
XV5 SUFFIX
5−LEAD PACKAGE
CASE 463B−01
ISSUE A
A
−X−
C
K
5
4
B
−Y−
S
12 3
D 5 PL
J
G
0.08 (0.003) M X Y
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE
MATERIAL.
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 1.50 1.70 0.059 0.067
B 1.10 1.30 0.043 0.051
C 0.50 0.60 0.020 0.024
D 0.17 0.27 0.007 0.011
G
0.50 BSC
0.020 BSC
J 0.08 0.18 0.003 0.007
K 0.10 0.30 0.004 0.012
S 1.50 1.70 0.059 0.067
SOLDERING FOOTPRINT*
0.3
0.0118
1.35
0.0531
1.0
0.0394
0.45
0.0177
0.5 0.5
0.0197 0.0197
ǒ Ǔ _{SCALE 20:1}
mm
inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
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