MC74HC132A_06 Datasheet, PDF (5/10 Pages) ON Semiconductor – Quad 2−Input NAND Gate with Schmitt−Trigger Inputs High−Performance Silicon−Gate CMOS

MC74HC132A
AC ELECTRICAL CHARACTERISTICS (C_L = 50 pF, Input t_r = t_f = 6.0 ns)
V_CC
Guaranteed Limit
Symbol
Parameter
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tPLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^tPHL
Maximum Propagation Delay, Input A or B to Output Y
(Figures 3 and 4)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _tTLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ t_THL
Maximum Output Transition Time, Any Output
(Figures 3 and 4)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Cin Maximum Input Capacitance}
V *55_C to 25_C v85_C v125_C Unit
2.0
125
4.5
25
6.0
21
155
190
ns
31
38
26
32
2.0
75
4.5
15
6.0
13
95
110
ns
19
22
16
19
—
10
10
10
pF
10. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High−Speed
CMOS Data Book (DL129/D).
Typical @ 25°C, V_CC = 5.0 V
C_PD Power Dissipation Capacitance (per Gate) (Note 11)
24
pF
11. Used to determine the no−load dynamic power consumption: P_D = C_PD V_CC2f + I_CC V_CC. For load considerations, see the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
INPUT
A OR B
Y
t_r
90%
50%
10%
t_PHL
90%
50%
10%
t_THL
t_f
V_CC
GND
t_PLH
t_TLH
Figure 3. Switching Waveforms
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
C_L*
*Includes all probe and jig capacitance
Figure 4. Test Circuit
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