MC74HC132A_06 Datasheet, PDF (1/10 Pages) ON Semiconductor – Quad 2−Input NAND Gate with Schmitt−Trigger Inputs High−Performance Silicon−Gate CMOS

MC74HC132A
Quad 2−Input NAND Gate
with Schmitt−Trigger Inputs
High−Performance Silicon−Gate CMOS
The MC74HC132A is identical in pinout to the LS132. The device
inputs are compatible with standard CMOS outputs; with pull−up
resistors, they are compatible with LSTTL outputs.
The HC132A can be used to enhance noise immunity or to square up
slowly changing waveforms.
Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements as Defined by JEDEC
Standard No. 7A
• Chip Complexity: 72 FETs or 18 Equivalent Gates
• Pb−Free Packages are Available
A1 1
B1 2
Y1 3
A2 4
B2 5
Y2 6
GND 7
14 V_CC
13 B4
12 A4
11 Y4
10 B3
9 A3
8 Y3
Figure 1. Pin Assignment
http://onsemi.com
MARKING
DIAGRAMS
14
PDIP−14
N SUFFIX
CASE 646
1
MC74HC132AN
AWLYYWWG
14
SOIC−14
D SUFFIX
CASE 751A
1
HC132AG
AWLYWW
TSSOP−14
DT SUFFIX
CASE 948G
14
HC
132A
ALYWG
G
1
14
SOEIAJ−14
F SUFFIX
CASE 965
1
74HC132A
ALYWG
A
= Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
FUNCTION TABLE
Inputs
A
B
L
L
L
H
H
L
H
H
Output
Y
H
H
H
L
© Semiconductor Components Industries, LLC, 2006
December, 2006 − Rev. 12
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
1
Publication Order Number:
MC74HC132A/D