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CM2030 Datasheet, PDF (5/17 Pages) California Micro Devices Corp – HDMI Transmitter Port Protection and Interface Device
CM2030
The internal accelerator increases the positive slew rate of the DDC_CLK_OUT and DDC_DAT_OUT lines
whenever the sensed voltage level exceeds 0.3*5V_SUPPLY (approximately 1.5V). This provides faster overall
risetime in heavily loaded situations without overloading the multi-drop open drain I2C outputs elsewhere.
DYNAMIC PULLUPS (CONT’D)
Figure 2. Dynamic DDC Pullups (Discrete - Top, CM2030 - Bottom; 3.3V ASIC - Left, 5V Cable - Right.)
Figure 2 demonstrates the “worst case” operation of the dynamic CM2030 DDC level shifting circuitry (bottom)
against a discrete NFET common-gate level shifter circuit with a typical 1.5kW pullup at the source (top.) Both
are shown driving an off-spec, but unfortunately readily available 31m HDMI cable which exceeds the 700pF
HDMI specification. Some widely available HDMI cables have been measured at over 4nF.
When the standard I/OD cell releases the NFET discrete shifter, the risetime is limited by the pullup and the
parasitics of the cable, source and sink. For long cables, this can extend the risetime and reduce the margin for
reading a valid “high” level on the data line. In this case, an HDMI source may not be able to read uncorrupted
data and will not be able to initiate a link.
With the CM2030’s dynamic pullups, when the ASIC driver releases its DDC line and the “OUT” line reaches at
least 0.3*VDD (of 5V_SUPPLY), then the “OUT” active pullups are enabled and the CM2030 takes over driving
the cable until the “OUT” voltage approaches the 5V_SUPPLY rail.
The internal pass element and the dynamic pullups also work together to damp reflections on the longer cables
and keep them from glitching the local ASIC.
I2C LOW LEVEL SHIFTING
In addition to the Dynamic Pullups described in the previous section, the CM2030 also incorporates improved
I2C low-level shifting on the DDC_CLK_IN and DDC_DAT_IN lines for enhanced compatibility.
Typical discrete NFET level shifters can advertise specifications for low RDS[on], but usually state relatively high
V[GS] test parameters, requiring a 'switch' signal (gate voltage) as high as 10V or more. At a sink current of 4mA
for the ASIC on DDC_XX_IN, the CM2030 guarantees no more than 140mV increase to DDC_XX_OUT, even
with a switching control of 2.5V on LV_SUPPLY.
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