CAV24C256WE-GT3 Datasheet, PDF (5/11 Pages) ON Semiconductor – 256-Kb I2C CMOS Serial EEPROM

CAV24C256
SCL
SDA
START
CONDITION
Figure 2. Start/Stop Timing
STOP
CONDITION
1
0
1
0 A₂ A₁ A₀ R/W
DEVICE ADDRESS
Figure 3. Slave Address Bits
SCL FROM
MASTER
BUS RELEASE DELAY (TRANSMITTER)
1
8
BUS RELEASE DELAY (RECEIVER)
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACK DELAY (≤ t_AA)
Figure 4. Acknowledge Timing
ACK SETUP (≥ t_SU:DAT)
SCL
t_SU:STA
SDA IN
t_F
t_HIGH
t_LOW
t_LOW
t_HD:STA
t_HD:DAT
t_R
t_SU:DAT
SDA OUT
t_AA
t_DH
Figure 5. Bus Timing
t_SU:STO
t_BUF
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5